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MIC3001
Micrel
MIC3001
SFP Management IC with Internal Calibration
General Description
The MIC3001 enables the implementation of sophisticated, hot-pluggable fiber optic transceivers with intelligent laser control and an internally calibrated Digital Diagnostic Monitoring Interface per SFF-8472. It essentially integrates all non-datapath functions of an SFP transceiver into a tiny 4mm x 4mm MLFTM package. It also works well as a microcontroller peripheral in transponders or 10Gbps transceivers. A highly configurable automatic power control (APC) circuit controls laser bias. Bias and modulation are temperature compensated using dual DACs, an on-chip temperature sensor, and NVRAM look-up tables. A programmable internal feedback resistor provides unprecedented dynamic range for APC. Controlled laser turn-on facilitates hot-plugging. An analog-to-digital converter converts the measured temperature, voltage, bias current, transmit power, and received power from analog to digital. An EEPOT provides frontend adjustment of RX power. Each parameter is compared against user-programmed warning and alarm thresholds. Analog comparators and DACs provide high-speed monitoring of received power and critical laser operating parameters. Data can be reported as either internally calibrated or externally calibrated. An interrupt output, power-on hour meter, and data-ready bits add user friendliness beyond SFF-8472. The interrupt output and data-ready bits reduce overhead in the host system. The power-on hour meter logs operating hours using an internal real-time clock and stores the result in NVRAM. Communication with the MIC3001 is via an industry standard 2-wire serial interface. Nonvolatile memory is provided for serial ID, configuration, and separate OEM and user scratchpad spaces. Two-level password protection guards against data corruption.
Features
* APC or constant-current laser bias * Turbo mode for APC loop start-up and shorter laser turn on time * Supports multiple laser types and bias circuit topologies * Drives external low-cost BJT for laser bias * Integrated digital temperature sensor * Temperature compensation of modulation, bias, and fault levels via NVRAM look-up tables * Direct interface to SY88932, SY88982, SY89307 and other drivers * NVRAM to support GBIC/SFP serial ID function * User writable EEPROM scratchpad * Diagnostic monitoring interface per SFF-8472 - Monitors and reports critical parameters: temperature, bias current, TX and RX optical power, and supply voltage - S/W control and monitoring of TXFAULT, RXLOS, RATESELECT, and TXDISABLE - Internal or external calibration - EEPOT for adjusting RX power measurement * Power-on hour meter * Interrupt capability * Extensive test and calibration features * 2-wire I2C compatible serial interface * SFP MSA and SFF-8472 compliant * 3.0V to 3.6V power supply range * 5V-tolerant I/O * 4mm x 4mm 24-pin MLFTM package
Applications
* * * * * * SFF/SFP optical transceivers SONET/SDH transceivers and transponders Fibre channel transceivers 10Gbps transceivers Free space optical communications Proprietary optical links
Ordering Information
Part Number MIC3001BML Junction Temp. Range -45C to +105C Package 24-pin MLFTM
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
Micrel, Inc. * 1849 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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Contents
General Description ............................................................................................................................................................................ 1 Features ............................................................................................................................................................................................... 1 Applications ......................................................................................................................................................................................... 1 Ordering Information .......................................................................................................................................................................... 1 Pin Configuration ................................................................................................................................................................................ 6 24-Lead MLFTM .................................................................................................................................................................................. 6 Pin Descriptions ............................................................................................................................................................................... 6-7 Absolute Maximum Ratings ............................................................................................................................................................... 8 Operating Ratings ............................................................................................................................................................................... 8 Electrical Characteristics .............................................................................................................................................................. 8-12 Timing Diagram ................................................................................................................................................................................. 12 Serial Interface Timing ..................................................................................................................................................................... 12 Address Map ...................................................................................................................................................................................... 13 Table 1. MIC3001 Address Map, Serial address = A0h .................................................................................................................. 13 Table 2. MIC3001 Address Map, Serial Address = A2h .................................................................................................................. 13 Table 3. Temperature Compensation Tables, Serial Address = A4h .............................................................................................. 14 Table 4. OEM Configuration Registers, Serial Address = A6h ........................................................................................................ 14 Block Diagram ................................................................................................................................................................................... 15 Figure 1. MIC3001 Block Diagram .................................................................................................................................................. 15 MIC3000 Compatibility ...................................................................................................................................................................... 15 Analog-to-Digital Converter/Signal Monitoring .............................................................................................................................. 15 Figure 2. Analog-to-Digital Converter Block Diagram ..................................................................................................................... 16 Table 5. A/D Input Signal Ranges and Resolutions ........................................................................................................................ 16 Table 6. VAUX Input Signal Ranges and Resolutions .................................................................................................................... 16 Internal/External Calibration ............................................................................................................................................................ 17 A/ External Calibration ...................................................................................................................................................................... 17 Voltage ............................................................................................................................................................................................... 17 Temperature ...................................................................................................................................................................................... 17 Bias Current ....................................................................................................................................................................................... 17 TX Power ............................................................................................................................................................................................ 17 RX Power ........................................................................................................................................................................................... 17 B/ Internal Calibration ....................................................................................................................................................................... 18 Table 8. Internal Calibration Coefficient Memory Map - Part I ........................................................................................................ 18 Table 7. LSB Values of Offset Coefficients ..................................................................................................................................... 18 Table 9. Internal Calibration Coefficient Memory Map - Part II ....................................................................................................... 19 C/ ADC Result Registers Reading ................................................................................................................................................... 19 RXPOT ................................................................................................................................................................................................ 20 Figure 3. RXPOT Block Diagram .................................................................................................................................................... 20 Laser Diode Bias Control ................................................................................................................................................................. 20 Figure 4. MIC3001 APC and Modulation Control Block Diagram .................................................................................................... 20 Figure 5. Programmable Feedback Resistor ................................................................................................................................... 20 Laser Modulation Control ................................................................................................................................................................. 20 Figure 6. Transmitter Configurations Supported by MIC3001 ......................................................................................................... 21 Figure 7. VMOD Configurations ...................................................................................................................................................... 21 Power ON and Laser Start-Up .......................................................................................................................................................... 22 Table 10. Shutdown State of SHDN vs. Configuration Bits ............................................................................................................. 22 Table 11. Shutdown State of VBIAS vs. Configuration Bits ............................................................................................................ 22 Table 12. Shutdown state of VMOD vs.. Configuration bits ............................................................................................................ 22 Figure 8. MIC3001 Power-On Timing (OE=1) ................................................................................................................................. 22 M9999-082404
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Fault Comparators ............................................................................................................................................................................ 23 Figure 9. Fault Comparator Logic .................................................................................................................................................... 23 SHDN and TXFIN ............................................................................................................................................................................... 23 Figure 10. Saturation Detector ........................................................................................................................................................ 24 Figure 11. RXLOS Comparator Logic ............................................................................................................................................. 24 Temperature Measurement .............................................................................................................................................................. 24 Diode Faults ....................................................................................................................................................................................... 24 Temperature Compensation ............................................................................................................................................................ 25 Table 13. Temperature Compensation Look-up Tables, Serial Address I2CADR + 4h .................................................................. 25 Table 14. APC Temperature Compensation Look-Up Table, Serial Address I2CADR+4h ............................................................. 26 Table 15. VMOD Temperature- Compensation Look-Up Table, Serial Address I2CADR+4h ........................................................ 26 Table 16. IBIAS Comparator Temperature Compensation Look-up Table, Serial Address I2CADR+4h ........................................ 26 Table 17. Bias Current High Alarm Temperature Compensation Table, Serial Address I2CADR+4h ............................................ 26 Table 18. Range of Temperature Compensation Tables vs. LUTOFF ............................................................................................ 27 Figure 12. Examples of LUTOFF Operation .................................................................................................................................... 27 Figure 13. Temperature Compensation Examples .......................................................................................................................... 28 Alarms and Warning Flags ............................................................................................................................................................... 29 Table 19. MIC3001 Events .............................................................................................................................................................. 29 Control and Status I/O ...................................................................................................................................................................... 29 Figure 14. Control and Status I/O Logic .......................................................................................................................................... 30 System Timing ................................................................................................................................................................................... 30 Figure 15. Transmitter ON-OFF Timing .......................................................................................................................................... 30 Figure 16. Initialization Timing with TXDISABLE Asserted ............................................................................................................. 30 Figure 17. Initialization Timing, TXDISABLE Not Asserted ............................................................................................................. 31 Figure 18. Loss-of-Signal (LOS) Timing .......................................................................................................................................... 31 Figure 19. Transmit Fault Timing .................................................................................................................................................... 31 Figure 20. Successfully Clearing a Fault Condition ......................................................................................................................... 32 Figure 21. Unsuccessful Attempt to Clear a Fault ........................................................................................................................... 32 Warm Resets ..................................................................................................................................................................................... 33 Power-On Hour Meter ....................................................................................................................................................................... 33 Table 20. Power-On Hour Meter Result Format .............................................................................................................................. 33 Test and Calibration Features ......................................................................................................................................................... 33 Table 21. Test and Diagnostic Features ......................................................................................................................................... 33 Serial Port Operation ........................................................................................................................................................................ 34 Figure 22. Write Byte Protocol ........................................................................................................................................................ 34 Figure 23. Read Byte Protocol ........................................................................................................................................................ 34 Figure 24. Read_Word Protocol ...................................................................................................................................................... 34 Page Writes ........................................................................................................................................................................................ 34 Figure 25. Four-Byte Page_Write Protocol ..................................................................................................................................... 35 Acknowledge Polling ........................................................................................................................................................................ 35 Write Protection and Data Security ................................................................................................................................................. 35 User Password .................................................................................................................................................................................. 35 Detailed Register Descriptions ........................................................................................................................................................ 36 Alarm Threshold Registers .............................................................................................................................................................. 36 Warning Threshold Registers .......................................................................................................................................................... 41 Checksum (CHKSUM) ....................................................................................................................................................................... 46 ADC Result Registers ....................................................................................................................................................................... 47 Alarm Flags ........................................................................................................................................................................................ 50 Warning Flags ................................................................................................................................................................................... 51 OEM Password Entry (OEMPW) ...................................................................................................................................................... 52 USER Password Setting (USRPWSET) ........................................................................................................................................... 52
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USER Password (USRPW) ............................................................................................................................................................... 53 Power-On Hours MSB (POHh) ......................................................................................................................................................... 53 Power-On Hours LSB (POHI) ........................................................................................................................................................... 53 Data Ready Flags (DATARDY) ......................................................................................................................................................... 54 USER Control Register (USRCTL) ................................................................................................................................................... 54 OEM Configuration Register 0 (OEMCFG0) .................................................................................................................................... 55 OEM Configuration Register 1 (OEMCFG1) .................................................................................................................................... 55 OEM Configuration Register 2 (OEMCFG2) .................................................................................................................................... 56 OAPC Setpoint 0 (APCSET0) ........................................................................................................................................................... 57 OAPC Setpoint 1 (APCSET1) ........................................................................................................................................................... 57 OAPC Setpoint 2 (APCSET2) ........................................................................................................................................................... 57 Modulation DAC Setting (MODSET) ................................................................................................................................................ 58 IBIAS Fault Threshold (IBFLT) ......................................................................................................................................................... 58 Transmit Power Fault Threshold (TXFLT) ....................................................................................................................................... 58 Loss-of-Signal Threshold (LOSFLT) ............................................................................................................................................... 58 Fault Suppresion Timer (FLTTMR) .................................................................................................................................................. 59 Fault Mask (FLMSK) .......................................................................................................................................................................... 59 OEM Password Setting (OEMPWSET) ............................................................................................................................................ 59 OEM Calibration 0 (OEMCAL0) ........................................................................................................................................................ 60 OEM Calibration 1 (OEMCAL1) ........................................................................................................................................................ 60 Look-Up Table Index (LUTINDX) ...................................................................................................................................................... 61 OEM Configuration 3 (OEMCFG3) ................................................................................................................................................... 61 BIAS DAC Setting (APCDAC) ........................................................................................................................................................... 62 Modulation DAC Setting (MODDAC) ............................................................................................................................................... 62 OEM Readback Register (OEMRD) .................................................................................................................................................. 62 Signal Detect Threshold (LOSFLTn) ............................................................................................................................................... 63 RX EEPOT Tap Selection (RXPOT) .................................................................................................................................................. 63 OEM Configuration 4 (OEMCFG4) ................................................................................................................................................... 63 Power-On Hour Meter Data (POHDATA) ......................................................................................................................................... 64 OEM Scratchpad Registers (SCRATCHn) ....................................................................................................................................... 64 RX Power Look-Up Table (RXLUTn) ................................................................................................................................................ 64 Calibration Constantts (CALn) ......................................................................................................................................................... 65 Manufacturer ID Register (MFG_ID) ................................................................................................................................................ 66 Device ID Register (DEV_ID) ............................................................................................................................................................ 66 Applications Information .................................................................................................................................................................. 67 Controlling Laser Diode Bias ........................................................................................................................................................... 67 Figure 26. Example APC Circuit for Common-Cathode TOSA ....................................................................................................... 67 Figure 27. Example APC Circuit for Common Anode TOSA ........................................................................................................... 67 Choosing CCOMP ............................................................................................................................................................................. 68 Figure 28. Slew Rate vs. CCOMP Value ........................................................................................................................................... 68 Figure 29. Open Loop Unity-Gain Bandwidth vs. CCOMP ............................................................................................................................................. 68 Table 22. Typical Values for CCOMP .................................................................................................................................................................................... 68 Measuring Laser Bias Current ......................................................................................................................................................... 68 Interfacing To Laser Drivers ............................................................................................................................................................ 68 SY88912 3.3V 3.2Gbps SONET/SDH Laser Driver .......................................................................................................................... 69 Figure 30. Controlling the SY88912 Modulation Current ................................................................................................................. 69 Table 23. Control Range of SY88912Modulation Control Circuit .................................................................................................... 69 SY88932 3.3V 3.2Gbps SONET/SDH Laser Driver .......................................................................................................................... 69 Figure 31. Controlling the SY88932 Modulation Current ................................................................................................................. 69 SY89307 5.0V/ 3.3V 2.5Gbps VCSEL Driver .................................................................................................................................... 70 Figure 32. Controlling the SY89307 Modulation Current ................................................................................................................. 70 M9999-082404
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Laser Drivers Programmed via a Sink Current .............................................................................................................................. 70 Figure 33. Controlling the Modulation Current via a Sink Current ................................................................................................... 70 Drivers With Monitor Outputs .......................................................................................................................................................... 70 Shutdown Output .............................................................................................................................................................................. 70 Figure 34. Redundant Switch Circuits ............................................................................................................................................. 71 Temperature Sensing ....................................................................................................................................................................... 71 Table 25. Contributors to Self-Heating ............................................................................................................................................ 71 Remote Sensing ................................................................................................................................................................................ 71 Table 24. Transistors Suitable for Use as Remote Diodes ............................................................................................................. 71 Minimizing Errors .............................................................................................................................................................................. 71 Self-Heating ....................................................................................................................................................................................... 71 Series Resistance with External Temperature Sensor .................................................................................................................. 72 XPN Filter Capacitor Selection ........................................................................................................................................................ 72 XPN Layout Considerations ............................................................................................................................................................. 72 Figure 35. Guard Traces and Kelvin Return for Remote Thermal Diode ........................................................................................ 72 Layout Considerations ..................................................................................................................................................................... 72 Small Form-Factor Pluggable (SFP) Transceivers ........................................................................................................................ 72 Figure 36. Typical SFP Control and Status I/O Signal Routing (not to scale) ................................................................................. 72 Power Supplies ................................................................................................................................................................................. 73 Figure 37. Power Supply Routing and Bypassing ........................................................................................................................... 73 Using The MIC3001 In a 5V System ................................................................................................................................................. 73 Package Information ......................................................................................................................................................................... 74 24-Pin MLFTM (ML) ........................................................................................................................................................................... 74
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Pin Configuration
RSOUT/GPO VMOD+ VMOD- RXLOS
FB VMPD GNDA VDDA VILD- VILD+
1 2 3 4 5 6
24 23 22 21 20 19 18 17 16 15 14 13 7
SHDN/TXFIN
COMP
VBIAS
VDDD NC GNDD RSIN VIN CLK
8
VRX
9 10 11 12
TXFAULT TXDISABLE XPN DATA
24-Lead MLFTM
Pin Descriptions
Pin Number 1 Pin Name FB Pin Function Analog Input. Feedback voltage for the APC loop op-amp . Polarity and scale are programmable via the APC configuration bits. Connect to VBIAS if APC is not used. Analog Input. Multiplexed A/D converter input for monitoring transmitted optical power via a monitor photodiode. In most applications, VMPD will be connected directly to FB. The input range is 0 - VREF or 0 - VREF/4 depending on the setting of the APC configuration bits Ground return for analog functions. Power supply input for analog functions. Analog Input. Reference terminal for the multiplexed pseudo-differential A/D converter inputs for monitoring laser bias current via a sense resistor (VILD+ is the sensing input). Tie to VDD or GND to reference the voltage sensed on VILD+ to VDD or GND respectively. Limited common-mode voltage range, see "Applications Information" section for more details. Analog Input. Multiplexed A/D input for monitoring laser bias current via a sense resistor (signal input); accommodates inputs referenced to VDD or GND (see pin 5 description). Limited common-mode voltage range, see "Applications Information" section for more details. Digital output; Programmable polarity. When used as shutdown output (SHDN), asserted at the detection of a fault condition that can be used to activate a second series transistor in the laser current path, enhancing protection against single-point failures. When programmed as TXFIN, it is an input for external fault signals to be ORed with the internal fault sources to drive TXFAULT. Analog Input. Multiplexed A/D converter input for monitoring received optical power. The input range is 0 to VREF. A 5-bit programmable EEPOT on this pin provides for coarse calibration and ranging of the RX power measurement. Analog Input/Output. Optional connection to an external PN junction for sensing temperature at a remote location. The Zone bit in OEMCFG1 determines whether temperature is measured using the on-chip sensor or the remote PN junction.
2
VMPD
3 4 5
GNDA VDDA VILD-
6
VILD+
7
SHDN (TXFIN)
8
VRX
9
XPN
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Pin Descriptions
Pin Number 10 Pin Name TXFAULT Pin Function Digital Output; Open-Drain. A high level indicates a hardware fault impeding transmitter operation. The state of this input is always reflected in the TXFLT bit. Digital Input; Active High. The transmitter is disabled when this line is high or the STXDIS bit is set. The state of this input is always reflected in the TXDIS bit. Digital I/O; Open-drain. Bi-directional serial data input/output. Digital Input; Serial bit clock input. If bit 4 (IE) in USRCTL register is set to 0 (default), this pin is configured as analog input. If IE bit is set to 1, this pin is configured as open-drain output. Analog Input: Multiplexed A/D input for monitoring supply voltage. 0V to 5.5V input range. Open-drain output: outputs the internally generated interrupt signal /INT. Digital Input; Rate select input; ORed with rate select bit to determine the state of the RSOUT pin. The state of this pin is always reflected in the RSEL bit. Ground return for digital functions. No connection. This pin is used for test purposes and must be left unconnected. Power supply input for digital functions. Digital Output; Active-High/Open-Drain. Indicates the loss of the received signal as indicated by a level of received optical power below the programmed RXLOS comparator threshold; may be wire-ORed with external signals. Low indicates normal operation. RXLOS is deasserted when VRX > LOSFLTn. The LOS bit reflects the state of RXLOS whether driven by the MIC3001 or an external circuit. Digital Output. Open-Drain or push-pull. When used as rate select output, this output is controlled by the SRSEL bit ORed with RSIN input and is open drain only. When used as a general-purpose non-volatile output, it is controlled by the GPO configuration bits in OEMCFG3. Analog Output, compensation terminal. Connect a capacitor between this pin and GNDA or VDDA with appropriate value to tune the APC loop time constant to a desirable value. Analog Output. Buffered DAC output capable of sourcing or sinking up to 10mA under control of the APC function to drive an external transistor for laser diode D.C. bias. The output and feedback polarity are programmable to accommodate either a NPN or an PNP transistor to drive a commonanode or common-cathode laser diode. Analog Input. Inverting terminal of VMOD buffer op-amp. Connect to VMOD+ (gain = 1) or feedback resistors network to set a different gain Analog Output. Buffered DAC output to set the modulation current on the laser driver IC. Operates with either a 0- VREF or a (VDD-VREF) - VDD output swing so as to generate either a ground-referenced or a VDD referenced programmed voltage. A simple external circuit can be used to generate a programmable current for those drivers that require a current rather than a voltage input. See "Applications Information" section for more details.
11
TXDISABLE
12 13 14
DATA CLK VIN
15
RSIN
16 17 18 19
GNDD NC VDDD RXLOS
20
RSOUT (GPO)
21
COMP
22
VBIAS
23 24
VMOD- VMOD+
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Absolute Maximum Ratings(1)
Power Supply Voltage, VDD ................................................. +3.8V Voltage on CLK, DATA, TXFAULT, VIN, RXLOS, DISABLE, RSIN ...................................... -0.3V to +6.0V Voltage On Any Other Pin ..................... -0.3V to VDD+0.3V Power Dissipation, TA = 85C ..................................... 1.5W Junction Temperature (TJ) ........................................ 150C Storage Temperature (TS) ....................... -65C to +150C ESD Ratings(3) Human Body Model ................................................... 2kV Machine Model ........................................................ 300V Soldering (20sec) ...................................................... 260C
Operating Ratings(2)
Power Supply Voltage, VDDA/VDDD ................ +3.0V to +3.6V Ambient Temperature Range (TA) ........... -40C to +105C Package Thermal Resistance MLFTM (JA) ......................................................... 43C/W
Electrical Characteristics
For typical values, TA = 25C, VDDA = VDDD = +3.3V, unless otherwise noted. Bold values are guaranteed for +3.0V (VDDA = VDDD) 3.6V, T(min) TA T(max)(8) Symbol Power Supply IDD Supply Current CLK = DATA = VDDD = VDDA;TXDISABLE low; all DACs at full-scale; all A/D inputs at full-scale; all other pins open. CLK = DATA = VDDD = VDDA; TXDISABLE high; FLTDAC at full-scale; all A/D inputs at full-scale; all other pins open. VPOR VUVLO VHYST tPOR VREF VREF/VDDA Power-on Reset Voltage Under-Voltage Lockout Threshold Power-on Reset Hysteresis Voltage Power-on Reset Time Reference Voltage Voltage Reference Line Regulation -40C TA +105C(6) -40C TA Note 4 +105C(6) VDD > VPOR(4) 1.210 All registers reset to default values; A/D conversions initiated. Note 5 2.5 2.3 3.5 mA Parameter Condition Min Typ Max Units
2.3
3.5
mA
2.9 2.73 170 50 1.225 1.7 1 1
2.98
V V mV s
1.240
V mV/V
Temperature-to-Digital Converter Characteristics Local Temperature Measurement Error Remote Temperature Measurement Error tCONV tSAMPLE IF Conversion Time Sample Period
3 3
60 100
C C ms ms A A
Remote Temperature Input, XPN Current to External Diode(4) XPN at high level, clamped to 0.6V. XPN at low level, clamped to 0.6V. Voltage-to-Digital Converter Characteristics (VRX, VAUX, VBIAS, VMPD, VILD+/-) Voltage Measurement Error tCONV tSAMPLE Conversion Time Sample Period -40C TA +105C(6) Note 4 Note 4 1 7 192 12 400
2.0
10 100
% fs ms ms
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Electrical Characteristics
Symbol Parameter Condition -0.3 VDD 3.6V VIN = VDD or GND; VAUX = VIN Min Typ Max Units Voltage Input, VIN (Pin 14 used as an ADC Input) VIN ILEAK CIN Input Voltage Range Input Current Input Capacitance -40C TA +105C(6) Note 4 Note 4 0.5 GNDA 55 10 1 5.5 V A pF
Digital-to-Voltage Converter Characteristics (VMOD, VBIAS) Accuracy tCONV DNL Conversion Time Differential Non-linearity Error 2.0 20 1 % fs ms LSB
Bias Current Sense Inputs, VILD+, VILD- VILD IIN+ IIN- CIN Differential Input Signal Range, | VILD+ - VILD- | VILD+ input current VILD input current | VILD+ - VILD- | = 0.3V Input Capacitance
-
0
VREF/4 1
mV A A A pF
VILD referred to VDDA VILD referred to GND
-
-
+150 -150 10
APC Op Amp, FB, VBIAS, COMP GBW TCVOS VOUT ISC tSC PSRR Gain Bandwidth Product Input Offset Voltage Temperature Coefficient(4) Output Voltage Swing IOUT = 10mA, SRCE bit = 1 IOUT = -10mA, SRCE bit = 0 Output Short-Circuit Current Short Circuit Withstand Time Power Supply Rejection Ratio TJ 150C(4) GNDA VDDA-1.25 55 55 40 1 3 20 25 START = 01h START = 02h START = 04h START = 08h CIN Pin Capacitance 0.375 0.750 1.500 3.000 10 V/V V/s % ppm/C mA mA mA mA pF CCOMP = 20pF; Gain = 1 1 1 1.25 VDDA MHz V/C V V mA sec dB
CCOMP = 20pF; Gain = 1, to GND CCOMP = 20pF; Gain = 1, to VDD CCOMP = 20pF, Note 4 CCOMP = 20pF; Gain = 1
AMIN V/t RFB RFB/t ISTART
Minimum Stable Gain Slew Rate Internal Feedback Resistor Tolerance Internal Feedback Resistor Temperature Coefficient Laser Start-up Current Magnitude
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Electrical Characteristics
Symbol Parameter Condition Min Typ Max Units VMOD Buffer Op-Amp, VMOD+, VMOD- GBW TCVOS IBIAS VOUT ISC tSC PSRR Gain Bandwidth Input Offset Voltage Temperature Coefficient VMOD- Input Current Output Voltage Swing Output Short-Circuit Current Short Circuit Withstand Time Power Supply Rejection Ratio TJ 150C(4) CCOMP = 20pF; Gain = 1, to GND CCOMP = 20pF; Gain = 1, to VDD AMIN V/T CIN VIL VIH VOL VOH ILEAK CIN VIN VRX CIN ILEAK Minimum Stable Gain Slew Rate Pin Capacitance CCOMP = 20pF CCOMP = 20pF; Gain = 1 1 10 IOUT = 1mA GNDA+75 35 65 44 1 CCOMP = 20pF; Gain = 1 1 1 0.1 1 VDDA-75 MHz V/C A mV mA sec dB dB V/V V/s pF
Control and Status I/O, TXDISABLE, TXFAULT, RSIN, RSOUT(GPO), SHDN(TXFIN), RXLOS, /INT Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage (applies to SHDN only) Input Current Input Capacitance 10 IOL 3mA IOH 3mA 2.0 0.3 VDDD-0.3 1 0.8 V V V V A pF
Transmit Optical Power Input, VMPD Input Voltage Range Input Signal Range Note 4 BIASREF=0 BIASREF=1 Input Capacitance Input Current Note 4 GNDA 0 VDDA-VREF 10 VDDA VREF VDDA V V V pF A
1
Note 4 GNDA 0 RXPOT = 1Fh 32 20 25 00 RXPOT 1Fh RXPOT = 0 (disconnected) Note 4 10 -5 +5 VDDA VREF
Received Optical Power Input, VRX, RXPOT Input Voltage Range VRX RRXPOT(32) RXPOT RXPOT/T Valid Input Signal Range (ADC Input Range) End-to-End Resistance Resistor Tolerance Resistor Temperature Coefficient V V k % ppm/C % A pF A
VRX/VRXPOT Divider Ratio Accuracy ILEAK CIN ILEAK Input Current Input Capacitance Input Current
1 1
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Electrical Characteristics
Symbol Parameter Condition Min Typ Max Units s ms ms Control and Status I/O Timing, TXFAULT, TXDISABLE, RSIN, RSOUT, and RXLOS tOFF tON tINIT TXDISABLE Assert Time TXDISABLE De-assert Time Initialization Time From input asserted to optical output at 10% of nominal, CCOMP = 10nF. From input de-asserted to optical output at 90% of nominal, CCOMP = 10nF. From power on or transmitter enabled to optical output at 90% of nominal and TX_FAULT de-asserted.(4) From power on to APC loop enabled. From fault condition to TXFAULT assertion.(4) Length of time TXDISABLE must be asserted to reset fault condition. From loss of signal to RXLOS asserted. From signal acquisition to LOS de-asserted. From power on to valid analog parameter data available.(4) Time from input change to corresponding internal register bit set or cleared.(4) From an internal register bit set or cleared to corresponding output change.(4) 10 95 100 400 1 1 10 1 300
tINIT2 tFAULT tRESET tLOSS_ON tLOSS_OFF tDATA tPROP_IN tPROP_OUT
Power-on Initialization Time TXFAULT Assert Time Fault Reset Time RXLOS Assert Time RXLOS De-assert Time Analog Parameter Data Ready TXFAULT, TXDISABLE, RXLOS, RSIN Input Propagation Time TXFAULT, RSOUT, /INT Output Propagation Time
200 95
ms s s s s ms s s
Fault Comparators
FLTTMR
Fault Suppression Timer Clock Period Accuracy
Note 4
0.475 -3
0.5
0.525 +3
ms %F.S. s
tREJECT VSAT
Glitch Rejection Saturation Detection Threshold
Maximum length pulse that will not cause output to change state.(4) High level Low level
4.5 95 5
%VDDA %VDDA
Power-On Hour Meter Timebase Accuracy 0C TA +70C(4) -40C TA +105C Resolution Non-Volatile (FLASH) Memory tWR Write Cycle Time(7) Data Retention Endurance Minimum Permitted Number Write Cycles From STOP of a one to four-byte write transaction.(4) 100 10,000 13 ms years cycles Note 4 +5 +10 10 -5 -10 % % hours
Serial Data I/O Pin, DATA VOL VIL VIH ILEAK CIN Low Output Voltage IOL = 3mA IOL = 6mA Low Input Voltage High Input Voltage Input Current Input Capacitance Note 4 10 2.1 0.4 0.6 0.8 V V V V A pF
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Electrical Characteristics
Symbol Parameter Condition 2.7V VDD 3.6V 2.7V VDD 3.6V Note 4 2.1 Min Typ Max Units Serial Clock Input, CLK VIL VIH ILEAK CIN t1 t2 t3 t4 t5 tDATA Low Input Voltage High Input Voltage Input Current Input Capacitance 10 0.8 V V A pF s ns ns ns ns 400 ms
1
Serial Interface Timing(4) CLK (clock) Period Data in Setup Time to CLK High Data Out Stable After CLK Low DATA Low Setup Time to CLK Low Start Condition 2.5 100 300 100 100
DATA High Hold Time After CLK High Stop Condition Data Ready Time From power on to completion of one set of ADC conversions; analog data available via serial interface.
Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Devices are ESD sensitive. Handling precautions recommended. 4. Guaranteed by desing and/or testing of related parameters. Not 100% tested in production. 5. The MIC3000 will attempt to enter its shutdown state when VDD falls below VUVLO. This operation requires time to complete. If the supply voltage falls too rapidly, the operation may not be completed. 6. Does not include quantization error. 7. The MIC3001 will not respond to serial bus transactions during an EEPROM write-cycle. The host will receive a NACK during tWR. 8. Final test on outgoing product is performed at TA = +25C.
Timing Diagram
t1 CLK t4 DATA (Input) t3 DATA (Output) t2 t5
Serial Interface Timing
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Address Map
Address(s) 0 - 95 96 - 127 128 - 255 Field Size (Bytes) 96 32 128 Name Serial ID defined by SEP MSA Vendor Specific Reserved Description G-P NVRAM; R/W under valid OEM password. Vendor specific EEPROM Reserved for future use. G-P NVRAM; R/W under valid OEM password.
Table 1. MIC3001 Address Map, Serial address = A0h
Address HEX 00-27 28-37 38-5B 5C-5E 5F 60-69 6A-6D 6E 6F 70-71 72-73 74-75 76-77 78-7B 7C-7F 80-F7 F8-F9 FA FB FC-FD FE FF DEC 0-39 40-55 56 -91 92-94 95 96-105 106-109 110 111 112-113 114-115 116-117 118-119 120-123 124-127 128-247 248-249 250 251 252-253 254 255
Field Size (Bytes) 40 16 36 3 1 10 4 1 1 2 2 2 2 4 4 120 2 1 1 2 1 1
Name Alarm and Warning Thresholds Reserved Calibration Constants Reserved Checksum Analog Data Reserved Control/Status bits Reserved Alarm Flags Reserved Warning Flags Reserved OEMPW Vendor Specific User Scratchpad Reserved USRPWSET USRPW POH Data Ready Flags User Control
Description High/low limits for warning and alarms; write-able using OEM p/w; read-only otherwise. Reserved - do not write; reads undefined. Numerical constants for external calibration; writeable using OEM p/w; read-only otherwise. Reserved - do not write; reads undefined. G-P NVRAM; writeable using OEM p/w; read-only otherwise. Real time analog parameter data. Reserved for future definition of digitized analog input- do not write; reads undefined. Control and status bits. Reserved - do not write; reads undefined. Alarm status bits; read-only. Reserved-do not write; reads undefined. Warning status bits; read-only. Reserved - do not write; reads undefined. OEM password entry field. Vendor specific. Reserved-do not write; reads undefined. User writable EEPROM. G-P NVRAM; R/W using any valid password. Reserved - do not write; reads undefined. User password setting; read/write using any p/w; returns zero otherwise. Entry field for user password. Power-on hour meter result; read-only. Data ready bits for each measured parameter; read-only. End-user control and status bits.
Table 2. MIC3001 Address Map, Serial Address = A2h
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Address(s) HEX 00-3F 40-7F 80-BF C0-FF DEC 0-63 64-127 128-191 192-255 Field Size (Bytes) 64 64 64 64
Micrel
Name APCLUTn MODLUTn IFLTLUT EOLLUTn
Description A.P.C. temperature compensation L.U.T. VMOD temperature compensation L.U.T. Bias current fault threshold temperature compensation L.U.T. Bias current high alarm threshold temperature compensation L.U.T.
Table 3. Temperature Compensation Tables, Serial Address = A4h
Address HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C-0F 10 11 12 13 14 15 16 17 18 19 1A-1F 20-27 28-47 48-49 4A-57 59-7D 7E-FD FE FF DEC 0 1 2 3 4 5 6 7 8 9 10 11 12-15 16 17 18 19 20 21 22 23 24 25 26-31 32-39 40-71 72-73 74-87 88-125 126-253 254 255 Field Size (Bytes) 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 6 8 32 2 18 37 128 1 1
Name OEMCFG0 OEMCFG1 OEMCFG2 APCSET0 APCSET1 APCSET2 MODSET IBFLT TXPFLT LOSFLT FLTTMR FLTMSK OEMPWSET OEMCAL0 OEMCAL1 LUTINDX RESERVED APCDAC MODDAC OEMREAD LOSFLTn RXPOT OEMCFG4 RESERVED POHDATA RXLUT RESERVED CAL RESERVED SCRATCH MFG_ID DEV_ID
Description Control/status bits Control/status bits Control/status bits APC setpoint 0 APC setpoint 1 APC setpoint 2 Nominal modulation DAC setpoint Bias current fault-comparator threshold TX power fault threshold RX LOS fault-comparator threshold Fault comparator masking interval timer setting Fault source mask bits Password for access to OEM areas OEM calibration register 0 OEM calibration register 1 Look-up table index read-back Reserved - do not write; reads undefined Reads back current APC DAC setting Reads back current modulation DAC setting Reads back OEM calibration data LOS De-Assert threshold RXPOT tap selection I START selection bits Reserved - do not write; reads undefined Power-on hour meter scratchpad RX power calibration look-up table Reserved - do not write; reads undefined Internal calibration slope/offset data Reserved-do not write; reads undefined OEM scratchpad area Manufacturer identification (Micrel = 42) Device and die revision
Table 4. OEM Configuration Registers, Serial Address = A6h
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Block Diagram
MIC3001 TXFAULT TXDISABLE RSIN RSOUT(GPO) RXLOS INT TIMING CLOCK I2C DATA VMOD- MODULATION CONTROL VMOD+ STATEMACHINES APC VBIAS COMP FB
MEMORY ARBITRATION
FAULT DETECTION
SHDN(TXFIN)
VILD+ NVRAM REGISTERS SERIAL ID SCRATCH LUTs LASER CONTROL A-D CONVERTER & SIGNAL CONDITIONING VILD- VMPD VIN
RXPOT POWER-ON HOUR METER CLOCK & POR
VRX
TEMP SENSOR
XPN
Figure 1. MIC3001 Block Diagram
MIC3000 Compatibility In general, the MIC3001 is completely hardware and software backward-compatible with the MIC3000. Every feature available in the MIC3000 is still present in the MIC3001. New features have, of course, been added. The following differences between the MIC3000 and MIC3001 would be evident to host software: 1. Faults do not set alarm or warning bits as in the MIC3000. 2. RXOPl at register address 69h at serial address x2h now contains four bits of data rather than being fixed at zero as in the MIC3000.
Analog-to-Digital Converter/Signal Monitoring A block diagram of the monitoring circuit is shown below. Each of the five analog parameters monitored by the MIC3001 are sampled in sequence. All five parameters are sampled and the results updated within the tCONV internal given in the "Electrical Characteristics" section. In OEM Mode, the channel that is normally used to measure VIN may be assigned to measure the level of the VDDA pin or one of five other nodes. This provides a kind of analog loopback for debug and test purposes. The VAUX bits in OEMCFG0 control which voltage source is being sampled. The various VAUX channels are level-shifted differently depending on the signal source, resulting in different LSB values and signal ranges. See Table 5.
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VIN VDDA VMOD VBIAS APCDAC MODDAC FLTDAC VAUX[2:1] VMPD VRX VILD+ VILD- TEMP SENSOR 5-CH MUX TEMP SENSOR SIGMA-DELTA ADC 7-CH MUX
Micrel
Figure 2. Analog-to-Digital Converter Block Diagram
Channel TEMP VAUX VMPD
ADC Resolution (bits) 8 8 8
Conditions
Input Range (V) N/A See Table 6
LSB(1) 1C
GAIN = 0; BIASREF = 0 GAIN = 0; BIASREF = 1 GAIN = 1; BIASREF = 0 GAIN = 1; BIASREF = 1
GNDA - VREF VDDA - (VDDA - VREF) GNDA - VREF/4 VDDA - (VDDA - VREF/4) VDDA - (VDDA - VREF) GNDA - VREF 0 - VREF
4.77mV
1.17mV
VILD
8
VILD- = VDDA VILD- = GNDA RXPOT = 00
4.77mV
VRX
12
0.298mV
Table 5. A/D Input Signal Ranges and Resolutions
Note: 1. Assumes typical VREF value of 1.22V.
Channel VIN VDDA VBIAS VMOD APCDAC MODDAC FLTDAC
VAUX[2:0] 000 = 00h 001 = 01h 010 = 02h 011 = 03h 100 = 04h 101 = 05h 110 = 06h
Input Range (V) 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to VREF 0V to VREF 0V to VREF
LSB(1) (mV) 25.6mV 25.6mV 25.6mV 25.6mV 4.77mV 4.77mV 4.77mV
Table 6. VAUX Input Signal Ranges and Resolutions
Note: 1. Assumes typical VREF value of 1.22V.
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Internal/External Calibration The default mode of calibration in the MIC3001 is external calibration, for which INTCAL bit (bit 0 in OEMCF3 register) is set to 0. This mode is backward compatible with MIC3000. The internal calibration mode is selected by setting INTCAL bit to 1. A/ External Calibration The voltage and temperature values returned by the MIC3001's A/D converter are internally calibrated. The binary values of TEMPh:TEMPl and VOLTh:VOLTl are in the format called for by SFF-8472 under Internal Calibration. SFF-8472 calls for a set of calibration constants to be stored by the transceiver OEM at specific non-volatile memory locations, refer to SFF-8472 specifications for memory map of calibration coefficient. The MIC3001 provides the nonvolatile memory required for the storage of these constants. The Digital Diagnostic Monitoring Interface specification should be consulted for full details. Slopes and offsets are stored for use with voltage, temperature, bias current, and transmitted power measurements. Coefficients for a fourthorder polynomial are provided for use with received power measurements. The host system can retrieve these constants and use them to process the measured data. Since voltage and temperature require no calibration, the corresponding slopes should generally be set to unity and the offsets to zero.
Voltage
Micrel
Per SFF-8472, the value of the bias current LSB is 2A. The conversion factor, "slope", needed is therefore:
Slope = 1191.4A 2A x R SENSE = 595.7 / R SENSE
The tolerance of the sense resistor directly impacts the accuracy of the bias current measurement. It is recommended that the sense resistor chosen be 1% accurate or better. The offset correction, if needed, can be determined by shutting down the laser, i.e., asserting TXDISABLE, and measuring the bias current. Any non-zero result gives the offset required. The offset will be equal and opposite to the result of the "zero current" measurement.
TX Power
Transmit power is sensed via an external sense resistor as a voltage appearing at VMPD. It is assumed that this voltage is generated by a sense resistor carrying the monitor photodiode current. In most applications, the signal at VMPD will be feedback voltage on FB. The VMPD voltage may be measured relative to GND or VDDA depending on the setting of the BIASREF bit in OEMCFG1. The value returned by the A/D is therefore a voltage analogous to transmit power. The binary value in TXOPh (TXOPl is always zero) is related to transmit power by:
TXOPh TXOPh K x VREF K x (1220mV) 255 255 PTX (mW) = = RSENSE RSENSE = K x 4.75656 x TXOPh mW RSENSE
The voltage values returned by the MIC3001's A/D converter are internally calibrated. The binary values of VOLTh:VOLTl are in the format called for by SFF-8472 under Internal Calibration. Since VINh:VINl requires no processing, the corresponding slope should be set to unity and the offset to zero.
Temperature
(3)
The temperature values returned by the MIC3001's A/D converter are internally calibrated. The binary values of TEMPh:TEMPl are in the format called for by SFF-8472 under Internal Calibration. Since TEMPh:TEMPl requires no processing, the corresponding slope should be set to unity and the offset to zero.
Bias Current
For a given implementation, the value of RSENSE is known. It is either the value of the external resistor or the chosen value of RFB used in the application. The constant, K, will likely have to be determined through experimentation or closedloop calibration, as it depends on the monitoring photodiode responsivity and coupling efficiency. It should be noted that the APC circuit acts to hold the transmitted power constant. The value of transmit power reported by the circuit should only vary by a small amount as long as APC is functioning correctly.
RX Power
Bias current is sensed via an external sense resistor as a voltage appearing at VILD+ and VILD-. The value returned by the A/D is therefore a voltage analogous to bias current. Bias current, IBIAS, is simply VVILD/RSENSE. The binary value in IBIASh (IBIASl is always zero) is related to bias current by:
IBIASh (0.300V) 255 R SENSE
Received power is sensed as a voltage appearing at VRX. It is assumed that this voltage is generated by a sense resistor carrying the receiver photodiode current. The value returned by the A/D is therefore a voltage analogous to received power. The binary value in RXOPh (RXOPl is always zero) is related to received power by:
PRX (mW ) = K x VREF x RXOPh 255 = K x 1220mV x RXOPh 255 mW (4)
IBIAS =
(1)
The value of the least significant bit (LSB) of IBIASh is given by:
LSB(IBIASh) = 0.300V 300mV 1191.4 Amps = mA = A 255 x RSENSE 255 x RSENSE RSENSE
(2)
For a given implementation, the constant, K, will likely have to be determined through experimentation or closed-loop calibration, as it depends on the gain and efficiencies of the components upstream. In SFF-8472 implementations, the external calibration constants can describe up to a fourthorder polynomial in case K is nonlinear.
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B/ Internal Calibration If the INTCAL bit in OEMCFG3 is set to 1 (internal calibration selected), the MIC3001 will process each piece of data coming out of the A/D converter before storing the result in memory. Linear slope/offset correction will be applied on a per-channel basis to the measured values for voltage, bias current, TX power, and RX power. Only offset correction is applied to temperature. The user must store the appropriate slope/offset parameters in memory at the time of transceiver calibration. In the case of RX power, a look-up table is provided that implements eight-segment piecewise-linear correction. This correction may be performed as temperature compensation or as simple slope/offset correction. If static slope/offset correction for RX power is desired, the eight coefficient sets can simply be made the same. The memory maps for these coefficients are shown in Table 8 and Table 9. The slopes allow for the correction of gain errors. Each slope coefficient is an unsigned, sixteen-bit, fixed-point binary number in the format: [mmmmmmmm.llllllll], where m is a data bit (5) in the most-significant byte and l is a data bit in the least significant byte Slopes are always positive. The binary point is in between the two bytes, i.e., between bits 7 and 8. This provides a numerical range of 1/256 (0.00391) to 255 in steps of 1/256. The most significant byte is always stored in memory at the lower numerical address. The offsets correct for constant errors in the measured data. Each offset is a signed, sixteen-bit, fixed-point binary number. The bit-weights of the offsets are the same as that of the final results. In the case of temperature, the offset's least significant byte (LSB) is always zero since the MIC3001 does not deal with fractional temperature values. The sixteen bit offsets provide a numerical range of -32768 to +32767 for voltage, bias current, transmit power, and receive power. The numerical range for the temperature offset is -32513 (-128) to +32512 (+127) in increments of 256 (1). The format for offsets is:
Micrel
[Smmmmmmmllllllll], where S is the sign bit (6) (1 = positive, 0 = negative), m is a data bit in the most-significant byte and l is a data bit in the least significant byte The most significant byte is always stored in memory at the lower numerical address. Calibration of voltage, bias current, and TX power are performed using the following calculation: RESULTn = ADC_RESULTn x SLOPEn + (7) OFFSETn Calibration of temperature is performed using the following calculation: RESULT = ADC_RESULT + OFFSET (8) Calibration of RX power is performed using the following calculation: (9) RESULT = ADC_RESULT xSLOPE(m) + OFFSET(m) where m is the appropriate value from the RX power calibration look-up table. The results of these calculations are rounded to sixteen bits in length. If the seventeenth most significant bit is a one, the result is rounded up to the next higher value. If the seventeenth most significant bit is zero, the upper sixteen bits remain unchanged. The bit-weights of the offsets are the same as that of the final results. For SFF-8472 compatible applications, these bit-weights are given in Table 7.
Parameter Temperature Voltage Bias Current TX Power RX Power Magnitude of LSB 1.0C(1) 100V 2A 0.1W 0.1W
Table 7. LSB Values of Offset Coefficients
Note: 1. The LSByte of the temperature is always zero.
Address(es) HEX 48-49 4A-4B 4C-4D 4E-4F 50-51 52-53 54-55 56-57 DEC 72-73 74-75 76-77 78-79 80-81 82-83 84-85 86-87 Field Size 2 2 2 2 2 2 2 2 Name RESERVED TOFFh:TOFFl VSLPh:VSLPl VOFFh:VOFFl ISLPh:ISLPl IOFFh:IOFFl TXSLPh: TXSLPl TXOFFh: TXOFFl Description Reserved. (There is no slope for temperature.) Do not write; reads undefined. Temperature offset; signed fixed point; LSB is always zero; MSB is at lower physical address. Voltage slope; unsigned fixed-point; MSB is at lower physical address. Voltage offset; signed fixed point; MSB is at lower physical address. Bias current slope; unsigned fixed-point; MSB is at lower physical address. Bias current offset; signed fixed point; MSB is at lower physical address. TX power slope; unsigned fixed-point; MSB is at lower physical address. TX power offset; signed fixed point; MSB is at lower physical address.
Table 8. Internal Calibration Coefficient Memory Map - Part I
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Address(es) Hex 28-29 2A-2B 2C-2D 2E-2F 30-31 32-33 34-35 36-37 38-39 3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 Dec 40-41 42-43 44-45 46-47 48-49 5 0-51 52-53 54-55 56-57 58-59 60-61 62-63 64-65 66-67 68-69 70-71 Field Size 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Name RXSLP0h: RXSLP0l RXOFF0h: RXOFF0l RXSLP1h: RXSLP1l RXOFF1h: RXOFF1l RXSLP2h: RXSLP2l RXOFF2h: RXOFF2l RXSLP3h: RXSLP3l RXOFF3h: RXOFF3l RXSLP4h: RXSLP4l RXOFF4h: RXOFF4l RXSLP5h: RXSLP5l RXOFF5h: RXOFF5l RXSLP6h: RXSLP6l RXOFF6h: RXOFF6l RXOFF7h: RXOFF7l RXSLP7h: RXSLP7l Description RX power slope 0; unsigned fixed-point; MSB is at lower physical address.
Micrel
RX power offset 0; signed twos-complement; MSB is at lower physical address. RX power slope 1; unsigned fixed-point; MSB is at lower physical address. RX power offset 1; signed twos-complement; MSB is at lower physical address. RX power slope 2; unsigned fixed-point; MSB is at lower physical address. RX power offset 2; signed twos-complement; MSB is at lower physical address. RX power slope 3; unsigned fixed-point; MSB is at lower physical address. RX power offset 3; signed twos-complement; MSB is at lower physical address. RX power slope 4; unsigned fixed-point; MSB is at lower physical address. RX power offset 4; signed twos-complement; MSB is at lower physical address. RX power slope 5; unsigned fixed-point; MSB is at lower physical address. RX power offset 5; signed twos-complement; MSB is at lower physical address. RX power slope 6; unsigned fixed-point; MSB is at lower physical address. RX power offset 6; signed twos-complement; MSB is at lower physical address. RX power slope 7; signed twos-complement; MSB is at lower physical address. RX power slope 7; signed fixed-point; MSB is at lower physical address.
Table 9. Internal Calibration Coefficient Memory Map - Part II
C/ ADC Result Registers Reading In the present revision of MIC3001, the ADC result registers should be read as 16 bit registers under internal calibration while under external calibration they should be read as 8 bit
registers at the MSB address. For example, TX power should be read under internal calibration as 16 bits at address A2h: 66-67 and under external calibration as 8 bits at address A2h: 66h.
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RXPOT A programmable, non-volatile digitally controlled potentiometer is provided for adjusting the gain of the receive power measurement signal chain in the analog domain. Five bits in the RXPOT register are used to set and adjust the position of potentiometer. RXPOT functions as a programmable divider or attenuator. It is adjustable in steps from 1:1 (no divider action) down to 1/32 in steps of 1/32. If RXPOT is set to zero, the divider is bypassed completely. There will be no scaling of the input signal, and the resistor network will be disconnected from the VRX pin. At all other settings of RXPOT, there will be a 32k (typical) load seen on VRX.
VRX
DAC
VDD-OUT
Micrel
The APCCAL bit in OEMCAL0 is used to turn the APC function on and off. It will be turned off in the MIC3001's default state as shipped from the factory. When APC is on, the value in the selected APCSETx register is added to the signed value taken from the APC look-up table and loaded into the VBIAS DAC. When APC is off, the VBIAS DAC may be written directly via the VBIAS register, bypassing the look-up table entirely. This provides direct control of the laser diode bias during setup and calibration. In either case, the VBIAS DAC setting is reported in the APCDAC register. The APCCFG bits determine the DACs response to higher or lower numeric values.
VOUT
VBIAS COMP INV FB
R1 R2 32:1 MUX R3
GAIN APC Look-Up Table APCSET Temp Sensor RFB[2:0] BIASREF VMOD Look-Up Table MODSET
VOUT VDD
ADC
R30 R31 R32 RXPOT[4:0]
5
DAC
VDD-OUT
VMOD MODREF VMOD-
Figure 3. RXPOT Block Diagram Laser Diode Bias Control The MIC3001 can be configured to generate a constant bias current using electrical feedback, or regulate average transmitted optical power using a feedback signal from a monitor photodiode, see Figure 4. An operational amplifier is used to control laser bias current via the VBIAS output. The VBIAS pin can drive a maximum of 10mA. An external bipolar transistor provides current gain. The polarity of the op amp's output is programmable BIASREF in OEMCFG1 in order to accommodate either NPN or PNP transistors that drive common anode and common cathode laser, respectively. Additionally, the polarity of the feedback signal is programmable for use with either common-emitter or emitter-follower transistor circuits. Furthermore, the reference level for the APC circuit is selectable to accommodate electrical, i.e., current feedback, or optical feedback via a monitor photodiode. Finally, any one of seven different internal feedback resistors can be selected. This internal resistor can be used alone or in parallel with an external resistor. This wide range of adjustability (50:1) accommodates a wide range of photodiode current, i.e, wide range of transmitter output power. The APC operating point can be kept near the mid-scale value of the APC DAC, insuring maximum SNR, maximum effective resolution for digital diagnostics, and the widest possible DAC adjustment range for temperature compensation, etc. See Figure 5.
Figure 4. MIC3001 APC and Modulation Control Block Diagram
APC Op-Amp FB R7 R6 R5 51.2k 25.6k 12.8k RFB[2:0]
7
R4 6.4k
R3 3.2k
R2 1.6k
R1 0.8k
VDD
BIASREF
Figure 5. Programmable Feedback Resistor Laser Modulation Control As shown in Figure 4, a temperature-compensated DAC is provided to set and control the laser modulation current via an external laser driver circuit. MODREF in OEMCFG0 selects whether the VMOD DAC output swings up from ground or down from VDD. If the laser driver requires a voltage input to set the modulation current, the MIC3001's VMOD output can drive it directly. If a current input is required, a fixed resistor can be used between the driver and the VMOD output. Several different configurations are possible as shown in Figure 7.
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When APC is on, i.e., the APCCAL bit in OEMCAL0 is set to 0, the value corresponding to the current temperature is taken from the MODLUT look-up table, added to MODSET, and loaded into the VMOD DAC. When APC is off, the value in VMOD is loaded directly into the VMOD DAC, bypassing the look-up table entirely. This provides for direct modulation control for setup and calibration. The MODREF bit determines the DACs response to higher or lower numeric values.
VDD
Micrel
VMOD Configured As Buffered Voltage Output
VOUT
DAC
VDD-OUT
VMOD MODREF
VMOD-
Output Swing = 0 to VREF or VDDA to (VDDA-VREF)
VMOD Configured As Buffered Voltage Output
VOUT
DAC
VDD-OUT
VMOD MODREF
R1+R2 Gain = A = R2
Common-cathode with Common-anode with monitor photodiode monitor photodiode VDD
R1
VMOD- R2
Output Swing = 0 to (VREFxA)
Figure 7. VMOD Configured as Voltage Output with Gain
Common-anode Common-cathode
Figure 6. Transmitter Configurations Supported by MIC3001
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Power ON and Laser Start-Up When power is applied, the MIC3001 initializes its internal registers and state machine. This process takes tPOR, about 50s. Following tPOR, analog-to-digital conversions begin, serial communication is possible, and the POR bit and data ready bits may be polled. The first set of analog data will be available tCONV after tPOR. MIC3001s are shipped from the factory with the output enable bit, OE, set to zero, off. The MIC3001's power-up default state, therefore, is APC off, VBIAS, VMOD, and SHDN outputs disabled. VBIAS, VMOD, and SHDN will be floating (high impedance) and the laser diode, if connected, will be off. Once the device is incorporated into a transceiver and properly configured, the shutdown states of SHDN, VBIAS and VMOD will be determined by the state of the APC configuration and OE bits. Table 10, Table 11, and Table 12 illustrate the shutdown states of the various laser control outputs versus the control bits.
Configuration Bits OE 0 1 1 SPOL Don't Care 0 1 Shutdown State SHDN Hi-Z GND VDD Configuration Bits OE 0 1 1 INV Don't Care Don't Care Don't Care BIASREF Don't Care 0 1
Micrel
VBIAS Shutdown State VBIAS Hi-Z GND VDD
Table 11. Shutdown State of VBIAS vs. Configuration Bits
Configuration Bits OE 0 1 1 MODREF Don't Care 0 1 VMOD Shutdown State VMOD Hi-Z GND VDD
Table 12. Shutdown state of VMOD vs. Configuration bits In order to facilitate hot-plugging, the laser diode is not turned on until tINIT2 after power-on. Following tINIT2, and assuming TXDISABLE is not asserted, the DACs will be loaded with their initial values. Since tCONV is much less than tINIT2, the first set of analog data, including temperature, is available at tINIT2. Temperature compensation will be applied to the DAC values if enabled. APC will begin if OE is asserted. (If the output enable bit, OE, is not set, the VMOD, VBIAS, and SHDN outputs will float indefinitely.) Figure 8 shows the power-up
Table 10. Shutdown State of SHDN vs. Configuration Bits
tINIT VDD VPOR tPOR tCONV VDD VPOR tPOR tCONV tINIT
TXFAULT
TXFAULT TXDISABLE TXDISABLE SHDN
(1)
SHDN /DATA_READY
(1)
/DATA_READY
|VMOD| |VMOD| |VBIAS|
90% nominal output
|VBIAS|
(2)
TX Output tON TX Output
(a) MIC3001 Power-On, TXDISABLE not Asserted
(b) MIC3001 Power-On, TXDISABLE Asserted
Notes: 1. Polarity programmable; active-high shown. 2. Determined by loop response, e.g., CCOMP.
Figure 8. MIC3001 Power-On Timing (OE=1)
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timing of the MIC3001. If TXDISABLE is asserted at powerup, the VMOD and VBIAS outputs will stay in their shutdown states following MIC3001 initialization. A/D conversions will begin, but the laser will remain off. Fault Comparators In addition to detecting and reporting the events specified in SFF-8472, the MIC3001 also monitors five fault conditions: inadequate supply voltage, thermal diode faults, excessive bias current, excessive transmit power, and APC op-amp saturation. Comparators monitor these parameters in order to respond quickly to fault conditions that could indicate link failure or safety issues, see Figure 9. When a fault is detected, the laser is shut down and TXFAULT is asserted. Each fault source may be independently disabled using the FLTMSK register. FLTMSK is non-volatile, allowing faults to be masked only during calibration and testing or permanently.
VDDA Saturation Detector
Micrel
The MIC3001 can also except and respond to fault inputs from external devices. See "SHDN and TXFIN" section. A similar comparator circuit monitors received signal strength and asserts RXLOS when loss-of-signal is detected (Figure 11). RXLOS will be asserted when and if VRX drops below the level programmed in LOSFLT. Hysteresis is implemented such that RXLOS will be deasserted when VRX subsequently rises above the level programmed in LOSFLTn. The loss-ofsignal comparator may be disabled completely by setting the LOSDIS bit in OEMCFG3. Once the LOS comparator is disabled, an external device may drive RXLOS. The state of the RXLOS pin is reported in the CNTRL register regardless of whether it is driven by the internal comparator or by an external device. A programmable digital-to-analog converter provides the comparator reference voltages for monitoring received signal strength, transmit power, and bias current. Glitches less than 10s (typical) in length are rejected by the fault comparators. Since laser bias current varies greatly with temperature, there is a temperature compensation look-up table for the bias current fault DAC value. When a fault condition is detected, the laser will be immediately shutdown and TXFAULT will be asserted. The VMOD, VBIAS, and SHDN (if enabled) outputs will be driven to their shutdown state according to the state of the configuration bits. The shutdown states of VMOD, VBIAS, and SHDN versus the configuration bit settings are shown in Table 10, Table 11, and Table 12. SHDN and TXFIN SHDN and TXFIN are optional functions of pin 7. SHDN is an output function and is designed to drive a redundant safety switch in the laser current path. TXFIN is an input function and serves as an input for fault signals from external devices that must be reported to the host via TXFAULT. The SHDN function is designed for applications in which the MIC3001 is performing all APC and laser management tasks. The TXFIN function is for situations in which an external device such as a laser diode driver IC is performing laser management tasks, including fault detection. If the TXFIN bit in OEMCFG3 is zero (the default mode), SHDN will be activated anytime the laser is supposed to be off. Thus, it will be active if 1) TXDISABLE is asserted, 2) STXDIS in CNTRL, is set, or 3) a fault is detected. SHDN is a push-pull logic output. Its polarity is programmable via the SPOL bit in OEMCFG1. If TXFIN is set to one, pin 7 serves as an input that accepts fault signals from external devices such as laser diode driver ICs. Multiple TXFAULT signals cannot simply be wire-ORed together as they are open-drain and active high. The input polarity is programmable via the TXFPOL bit in OEMCFG3. TXFIN is logically ORed with the MIC3001's internal fault sources to produce TXFAULT and determine the value of the transmit fault bit in CNTRL. See Figure 9.
95% VDDA
5% VDDA
tFLTTMR VCOMP COUNTER FLTTMR
IBFLT
FLTDAC VILD
TXFAULT pin
VUVLO VDD
/LASER_SHUTDOWN TXFLT bit
TXPFLT
FLTDAC VMPD DIODE_FAULT
Figure 9. Fault Comparator Logic Thermal diode faults are detected within the temperature measurement subsystem when an out-of-range signal is detected. A window comparator circuit monitors the voltage on the compensation capacitor to detect APC op-amp saturation (Figure 10). Op-amp saturation indicates that some fault has occurred in the control loop such as loss of feedback. The saturation detector is blanked for a time, tFLTTMR, following laser turn-on since the compensation voltage will essentially be zero at turn-on. The FLTTMR interval is programmable from 0.5ms to 127ms (typical) in increments of 0.5ms (FLTTMR). Note that a saturation comparator cannot be relied upon to meet certain eye-safety standards that require 100s response times. This is because the operation of a saturation detector is limited by the loop bandwidth, i.e., the choice of CCOMP. Even if the comparator itself was very fast, it would be subject to the limited slew-rate of the APC op-amp. Only the other fault comparator channels will meet <100s timing requirements.
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VDDA
Saturation Detector
95% VDDA
5% VDDA SATURATION_FAULT
tFLTTMR VCOMP COUNTER FLTTMR
Figure 10. Saturation Detector
CNTRL LOS
OEMCFG3 LOS DIS VDDA VRX LOSFLT LOSFLTn
D1
RXLOS
D0
2:1 MUX
FLTDAC
Figure 11. RXLOS Comparator Logic
Temperature Measurement The temperature-to-digital converter for both internal and external temperature data is built around a switched current source and an eight-bit analog-to-digital converter. The temperature is calculated by measuring the forward voltage of a diode junction at two different bias current levels. An internal multiplexer directs the current source's output to either an internal or external diode junction. The value of the ZONE bit in OEMCFG1 determines whether readings are taken from the on-chip sensor or from the XPN input. The external PN junction may be embedded in an integrated circuit, or it may be a diode-connected discrete transistor. This data is also used as the input to the temperature compensation look-up tables. Each time temperature is sampled and an updated value acquired, new corrective values for IMOD and the APC setpoint are read from the corresponding tables, added to the set values, and transferred to DACs.
Diode Faults The MIC3001 is designed to respond in a failsafe manner to hardware faults in the temperature sensing circuitry. If the connection to the sensing diode is lost or the sense line is shorted to VDD or ground, the temperature data reported by the A/D converter will be forced to its full-scale value (+127C). The diode fault flag, DFLT, will be set in OEMCFG1, TXFAULT will be asserted, and the high temperature alarm and warning flags will be set. The reported temperature will remain +127C until the fault condition is cleared. Diode faults may be reset by toggling TXDISABLE, as with any other fault. Diode faults will not be detected at power up until the first A/D conversion cycle is completed. Diode faults are not reported while TXDISABLE is asserted.
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Temperature Compensation Since the performance characteristics of laser diodes and photodiodes change with operating temperature, the MIC3001 provides a facility for temperature compensation of the A.P.C. loop setpoint, laser modulation current, bias current fault comparator threshold, and bias current high alarm flag threshold. Temperature compensation is performed using a look-up table (LUT) that stores values corresponding to each measured temperature over a 128C span. Four identical tables reside at serial address A4h as summarized in Table 13. The range of temperatures spanned by the tables is programmable via the LUTOFF register. Each table entry is a signed twos complement number that is used as an offset to the parameter being compensated. The default value of all table entries is zero, giving a flat response. The A/D converter reports a new temperature sample each tCONV. This occurs at roughly 10Hz. To prevent temperature oscillation due to thermal or electrical noise, sixteen successive temperature samples are averaged together and used to index the LUTs. Temperature compensation results are therefore updated at 16xtCONV intervals, or about 1.6 seconds. This can be expressed as shown in Equation10.
TCOMPm = Tn + Tn +1 + Tn + 2 + * * *Tn +15 16 = APCSETx + APCLUT(TCOMPm )
Table _ min TCOMPm Table _ max
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APCSETm APCSETm APCSETm
= APCSETx + APCLUT(max)
TCOMP > Table _ max
= APCSETx + APCLUT(min)
TCOMP < Table _ min
(11)
If the measured temperature is greater than the maximum table value, the highest value in each table is used. If the measured temperature is less than the minimum, the minimum value is used. Hysteresis is employed to further enhance noise immunity and prevent oscillation about a table threshold. Each table entry spans two degrees C. The table index will not change unless the new temperature average results in a table index beyond the midpoint of the next entry in either direction. There is therefore 2 to 3C of hysteresis on temperature compensation changes. The table index will never oscillate due to quantization noise as the hysteresis is much larger than 12 LSB.
Byte Addresses 00h-3Fh 40h-7Fh 80h-BFh C0h-FFh Function APC Look-up Table IMOD Look-up Table IFLT Look-up Table Bias High Alarm Look-up Table
(10)
Each time an updated average value is acquired, a new offset value for the APC setpoint is read from the corresponding look-up table (see Table 14) and transferred to the APC circuitry. This is illustrated in Equation 11. In a same way, new offset values are taken from similar look-up tables (see Table 15 and Table 16), added to the nominal values and transferred into the modulation and fault comparator DACs. The bias current high alarm threshold, is compensated using a fourth look-up table (see Table 17). This compensation happens internally and does not affect any host-accessible registers.
Table 13. Temperature Compensation Look-up Tables, Serial Address I2CADR + 4h
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Register Address 00 h Table Offset 0 Temperature Offset (C) 0 1 01h 1 2 3 02h 2 4 5 * * * 3Eh * * * 62 * * * 124 125 3Fh 63 126 127 BFh 63 * * * BEh * * * 62 82h 2 81h 1 Register Address 80 h Table Offset 0
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Temperature Offset (C) 0 1 2 3 4 5 * * * 124 125 126 127
Table 14. APC Temperature Compensation Look-Up Table, Serial Address I2CADR+4h
Register Address 40 h Table Offset 0 Temperature Offset (C) 0 1 41h 1 2 3 42h 2 4 5 * * * 7Eh * * * 62 * * * 124 125 7Fh 63 126 127
Table 16. IBIAS Comparator Temperature Compensation Look-up Table, Serial Address I2CADR+4h
Register Address CO h Table Offset 0 Temperature Offset (C) 0 1 C1h 1 2 3 C2h 2 4 5 * * * FEh * * * 62 * * * 124 125 FFh 63 126 127
Table 15. VMOD Temperature- Compensation Look-Up Table, Serial Address I2CADR+4h
Table 17. Bias Current High Alarm Temperature Compensation Table, Serial Address I2CADR+4h
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The LUTOFF register determines the range of measured temperatures that are actually spanned by the tables. The temperature span of the tables versus the value of LUTOFF is given in Table 18.
Temperature Span tCOMP(min) - tCOMP(max) 0C to +127C -2C to +125C -4C to +123C * * * -30C to +97C INDEX = TAVG(n) 2 + LUTOFF
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(12)
where TAVG(n) is the current average temperature; and
TABLE _ ADDRESS = INDEX + BASE _ ADDRESS
LUTOFF 00h 01h 02h * * * 0Fh
Table 18. Range of Temperature Compensation Tables vs. LUTOFF The internal state machine calculates a new table index each time a new average temperature value becomes available. This table index is derived from the average temperature value and LUTOFF. The table index is then converted into a table address for each of the four look-up tables. These operations can be expressed as:
where BASE_ADDRESS is the physical base address of each table, i.e., 00h, 40h, 80h, or C0h (all tables reside in the I2CADR+4 page of memory). At any given time, the current table index can be read in the LUTINDX register. Figures 12 and 13 illustrate the operation of the temperature compensation tables. Figure 12 is a graphical illustration of the use of the LUTOFF register to control the temperature range spanned by the temperature compensation tables. Note that, if the LUTINDX becomes greater than 63 or less than zero, the maximum or minimum table value is used, respectively. The tables do not "roll over."
LUT(LUTINDX)
+127
(a)
0
63
-128
LUT(t), LUTOFF=0
+127
LUT(t), LUTOFF=07h
+127
LUT(t), LUTOFF=0Fh
+127
(b)
-30C
0
+127C
(c)
-30C
0
+127C
(d)
-30C
0
+127C
+113C
+98C
-128
-128
-128
Figure 12. Examples of LUTOFF Operation
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Figure 13 llustrates that the table values are used as offsets to the nominal value of the parameter in question. APCSET is used as an example, but all four tables function identically.
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Note that the shape and magnitude of the compensation curve do not change as the nominal value changes.
LUT(LUTINDX)
+127
(a)
0
63
LUTOFF = 0Fh APCSEL = 00h
-128
+127
+127
+127
(b)
(c)
(d)
-40C
0 +34C
+127C +98C
-40C
0 +34C
+127C +98C
-40C
0 +34C
+127C +98C
APCSET0 = 64
APCSET0 = 92
APCSET0 = 128
Figure 13. Temperature Compensation Examples
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Alarms and Warning Flags There are twenty different conditions that will cause the MIC3001 to set one of the bits in the WARNx or ALARMx registers. These conditions are listed in Table 19. The less critical of these events generate warning flags by setting a bit in WARN0 or WARN1. The more critical events cause bits to be set in ALARM0 or ALARM1. An event occurs when any alarm or warning condition becomes true. Each event causes its corresponding status bit in ALARM0, ALARM1, WARN0, or WARN1 to be set. This action cannot be masked by the host. The status bit will remain set until the host reads that particular status register, a power on-off cycle occurs, or the host toggles TXDISABLE. If TXDISABLE is asserted at any time during normal operation, A/D conversions continue. The A/D results for all parameters will continue to be reported. All events will be reported in the normal way. If they have not already been individually cleared by read operations, when TXDISABLE is deasserted, all status registers will be cleared.
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Control and Status I/O The logic for the transceiver control and status I/O is shown schematically in Figure 14. Note that the internal drivers on RXLOS, RATE_SELECT, and TXFAULT are all open-drain. These signals may be driven either by the internal logic or external drivers connected to the corresponding MIC3001 pins. In any case, the signal level appearing at the pins of the MIC3001 will be reported in the control register status bits. Note that the control bits for TX_DISABLE and RATE_SELECT and the status bits for TXFAULT and RXLOS do not meet the timing requirements specified in the SFP MSA or the GBIC Specification, revision 5.5 (SFF-8053) for the hardware signals. The speed of the serial interface limits the rate at which these functions can be manipulated and/or reported. The response time for the control and status bits is given in the "Electrical Characteristics" section.
Event Temperature high alarm Temperature low alarm Voltage high alarm Voltage low alarm TX bias high alarm TX bias low alarm TX power high alarm TX power low alarm RX power high alarm RX power low alarm Temperature high warning Temperature low warning Voltage high warning Voltage low warning TX bias high warning TX bias low warning TX power high warning TX power low warning RX power high warning RX power low warning
Condition TEMP > TMAX TEMP < TMIN VIN > VMAX VIN < VMIN IBIAS > IBMAX IBIAS < IBMIN TXOP > TXMAX TXOP < TXMIN RXOP > RXMAX RXOP < RXMIN TEMP > THIGH TEMP < TLOW VIN > VHIGH VIN < VLOW IBIAS > IBHIGH IBIAS < IBLOW TXOP > TXHIGH TXOP < TXLOW RXOP > RXHIGH RXOP < RXLOW Table 19. MIC3001 Events
MIC3001 Response Set ALARM0[7] Set ALARM0[6] Set ALARM0[5] Set ALARM0[4] Set ALARM0[3] Set ALARM0[2] Set ALARM0[1] Set ALARM0[0] Set ALARM1[7] Set ALARM1[6] Set WARN0[7] Set WARN0[6] Set WARN0[5] Set WARN0[4] Set WARN0[3] Set WARN0[2] Set WARN0[1] Set WARN0[0] Set WARN1[7] Set WARN1[6]
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D7 D6 D5 D4 D3 D2 D1 D0
TXDISABLE
LASER_SHUTDOWN
RSIN
RSOUT
TXFAULT ILD & TX Fault Comparators RXLOS RXLOS Fault Comparator
Figure 14. Control and Status I/O Logic
System Timing
The timing specifications for MIC3001 control and status I/O are given in the "Electrical Characteristics" section.
TXDISABLE tOFF
90% of nominal output
tON
Transmitter Output
10% of nominal output
TXFAULT
Figure 15. Transmitter ON-OFF Timing
tINIT
VDD
tPOR
TXFAULT
TXDISABLE
90% Nominal Output
Transmitter Output
Figure 16. Initialization Timing with TXDISABLE Asserted
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VDD
TXFAULT
TXDISABLE
90% Nominal Output
Transmitter Output tINIT
Figure 17. Initialization Timing, TXDISABLE Not Asserted
Loss of Signal tLOSS_ON RXLOS tLOSS_OFF
Transmitter Output
Figure 18. Loss-of-Signal (LOS) Timing
Occurance of Fault tFAULT TXFAULT
Transmitter Output
10% of Nominal Output
Figure 19. Transmit Fault Timing
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tRESET TXDISABLE tINIT TXFAULT
Transmitter Output
90% of Nominal Output
Figure 20. Successfully Clearing a Fault Condition
Fault Condition
tRESET TXDISABLE tINIT TXFAULT tFAULT Transmitter Output
10% of Nominal Output
Figure 21. Unsuccessful Attempt to Clear a Fault
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Warm Resets The MIC3001 can be reset to its power-on default state during operation by setting the reset bit in OEMCFG0. When this bit is set, TXFAULT and RXLOS will be deasserted, all registers will be restored to their normal power-on default values, and any A/D conversion in progress will be halted and the results discarded. The state of the MIC3001 following this operation is indistinguishable from a power-on reset. Power-On Hour Meter The Power-On Hour meter logs operating hours using an internal real-time clock and stores the result in NVRAM. The hour count is incremented at ten-hour intervals in the middle of each interval. The first increment therefore takes place five hours after power-on. Time is accumulated whenever the MIC3001 is powered. The hour meter's timebase is accurate to 5% over all MIC3001 operating conditions. The counter is capable of storing counts of more than thirty years, but is ultimately limited by the write-cycle endurance of the nonvolatile memory. This implies a range of at least twenty years.
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Actual results will depend on the operating conditions and write-cycle endurance of the part in question. Two registers, POHH and POHl, contain a 15-bit power-on hour measurement and an error flag, POHFLT. Great care has been taken to make the MIC3001's hour meter immune to data corruption and to insure that valid data is maintained across power cycles. The hour meter employs multiple data copies and error correction codes to maintain data validity. This data is stored in the POHDATA registers. If POHFLT is set, however, the power-on hour meter data has been corrupted and should be ignored. It is recommended that a two-byte (or more) sequential read operation be performed on POHh and POHl to insure coherency between the two registers. These registers are accessible by the OEM using a valid OEM password. The only operation that should be performed on these registers is to clear the hour meters initial value, if necessary, at the time of product shipment. The hour meter result may be cleared by setting all eight POHDATA bytes to 00h.
Power-On Hour Result Format High Byte, POHH Error flag Elapsed Time / 10 Hours, MSB's MSB Low Byte, POHl Elapsed Time / 10 Hours, LSB's LSB Table 20. Power-On Hour Meter Result Format
Test and Calibration Features Numerous features are included in the MIC3001 to facilitate development, testing, and diagnostics. These features are
Function Analog loop-back Fault comparator disable control Fault comparator spin-on-channel mode Fault comparator output read-back RSOUT, /INT read-back Inhibit EEPROM write cycles APC calibration mode Continuity checking Halt A/D ADC idle flag A/D one-shot mode A/D spin-on-channel mode Channel selection LUT index read-back Manufacturer and device ID registers Description
available via registers in the OEM area. As shown in Table 21, these features include:
Control Register(s) OEMCFG0 OEMCAL0 OEMCAL0 OEMRD OEMRD OEMCAL0 OEMCAL0 OEMCAL0 OEMCAL1 OEMCAL1 OEMCAL1 OEMCAL1 OEMCAL1 LUTINDX MFG_ID, DEV_ID
Provides analog visibility of op-amp and DAC outputs via the ADC Disables the fault comparator Selects a single fault comparator channel Allows host to read individual fault comparator outputs Allows host to read the state of these pins Speeds repetitive writes to registers backed up by NVRAM Allows direct writes to MODDAC and APCDAC (temperature compensation not used) Forcing of RXLOS, TXFAULT, /INT Stops A/D conversions; ADC in one-shot mode Indicates ADC status Performs a single A/D conversion on the selected input channel Selects a single input channel Selects ADC or fault comparator channel for spin-on-channel modes Permits visibility of the LUT index calculated by the state-machine Facilitates presence detection and version control
Table 21. Test and Diagnostic Features
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Serial Port Operation The MIC3001 uses standard Write_Byte, Read_Byte, and Read_Word operations for communication with its host. It also supports Page_Write and Sequential_Read transactions. The Write_Byte operation involves sending the device's slave address (with the R/W bit low to signal a write operation), followed by the address of the register to be operated upon and the data byte. The Read_Byte operation is a composite write and read operation: the host first sends the device's slave address followed by the register address, as in a write operation. A new start bit must then be sent to the MIC3001, followed by a repeat of the slave address with the R/W bit (LSB) set to the high (read) state. The data to be read from the part may then be clocked out. A Read_Word is similar, but two successive data bytes are clocked out rather than one. These protocols are shown in Figure 22 to 25. The MIC3001 will respond to up to four sequential slave addresses depending on whether it is in OEM or User mode. A match between one of the MIC3001's addresses and the address specified in the serial bit stream must be made to initiate communication. The MIC3001 responds to slave addresses A0h and A2h in User Mode; it also responds to A4h and A6h in OEM Mode (assuming I2CADR = Axh).
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Page Writes To increase the speed of multi-byte writes, the MIC3001 allows up to four consecutive bytes (one page) to be written before the internal write cycle begins. The entire non-volatile memory array is organized into four-byte pages. Each page begins on a register address boundary where the last two bits of the address are 00b. Thus the page is composed of any four consecutive bytes having the addresses xxxxxx00 b, xxxxxx01b, xxxxxx10b, and xxxxxx11b. The page write sequence begins just like a Write_Byte operation with the host sending the slave address, R/W bit low, register address, etc. After the first byte is sent the host should receive an acknowledge. Up to three more bytes can be sent in sequence. The MIC3001 will acknowledge each one and increment its internal address register in anticipation of the next byte. After the last byte is sent, the host issues a STOP. The MIC3001's internal write process then begins. If more than four bytes are sent, the MIC3001's internal address counter wraps around to the beginning of the four-byte page. To accelerate calibration and testing, NVRAM write cycles can be disabled completely by setting the WRINH bit in OEMCAL0. Writes to registers that do not have NVRAM backup will not incur write-cycle delays when writes are inhibited. Write operations on registers that exist only in NVRAM will still incur write cycle delays.
MIC3001 Slave Address
Register Address
Data Byte to MIC3001
DATA S 1 0 1 0 0 0 0 0 A X X X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 /A P
START R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE NOT ACKNOWLEDGE STOP
CLK Master to slave transfer, i.e., DATA driven by master. Slave to master transfer, i.e., DATA driven by slave.
Figure 22. Write Byte Protocol
MIC3001 Slave Address Register Address MIC3001 Slave Address Data Read From MIC3001
DATA S 1 0 1 0 0 0 0 0 A 0 0 X X X X X X A S 1 0 0 1 X X A0 1 A X X X X X X X X /A P
START R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE START R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE STOP
CLK Master to slave transfer, i.e., DATA driven by master. Slave to master transfer, i.e., DATA driven by slave.
Figure 23. Read Byte Protocol
High-Order Byte from MIC3001 Low-Order Byte from MIC3001
MIC3001 Slave Address
Register Address
MIC3001 Slave Address
DATA S 1 0 1 0 0 0 0 0 A 0 0 0 0 0 0 X X A S 1 0 1 0 0 0 0 1 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 /A P
START R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE START R/W = READ ACKNOWLEDGE ACKNOWLEDGE NOT ACKNOWLEDGE STOP
CLK Master-to-slave tranfer, i.e., DATA driven by master. Slave-to-master transfer, i.e.,DATA driven by slave.
Figure 24. Read_Word Protocol
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MIC3001 Slave Address
Register Address
1st Data Byte to MIC3001
2nd Data Byte to MIC3001
DATA S 1 0 1 0 0 0 0 0 A X X X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 * * *
START R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE ACKNOWLEDGE
CLK 3rd Data Byte to MIC3001 4th Data Byte to MIC3001
***
* * * D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 /A P
R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE STOP
*** Master to slave transfer, i.e., DATA driven by master. Slave to master transfer, i.e., DATA driven by slave.
Figure 25. Four-Byte Page_Write Protocol
Acknowledge Polling The MIC3001's non-volatile memory cannot be accessed during the internal write process. To allow for maximum speed bulk writes, the MIC3001 supports acknowledge polling. The MIC3001 will not acknowledge serial bus transactions while internal writes are in progress. The host may therefore monitor for the end of the write process by periodically checking for an acknowledgement. Write Protection and Data Security OEM Password A password is required to access the OEM areas of the MIC3001, specifically the non-volatile memory, look-up tables, and registers at serial addresses A4h and A6h. A four-byte field, OEMPWSET, at serial address A6h is used for setting the OEM password. The OEM password is set by writing OEMPWSET with the new value. The password comparison is performed following the write to the MSB of the OEMPW, address 7Bh at serial address A2h. Therefore, this byte must be written last! A four-byte burst-write sequence to address 78h may be used as this will result in the MSB being written last. The new password will not take effect until after a power-on reset occurs or a warm reset is performed using the RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. The corresponding four-byte field for password entry, OEMPW, is located at serial address A2h. This field is therefore always visible to the host system. OEMPW is compared to the fourbyte OEMPWSET field at serial address A6h. If the two fields match, access is allowed to the OEM areas of the MIC3001 non-volatile memory at serial addresses A4h and A6h. If OEMPWSET is all zeroes, no password security will exist. The value in OEMPW will be ignored. This helps prevent a deliberately unsecured MIC3001 from being inadvertently locked. Once a valid password is entered, the MIC3001 OEM areas will be accessible. The OEM areas may be re-secured
by writing an incorrect password value at OEMPW, e.g., all zeroes. In all cases OEMPW must be written LSB first through MSB last. The OEM areas will be inaccessible following the final write operation to OEMPW's LSB. The OEMPW field is reset to all zeros at power on. Any values written to these locations will be readable by the host regardless of the locked/unlocked status of the device. If OEMPWSET is set to zero (00000000h), the MIC3001 will remain unlocked regardless of the contents of the OEMPW field. This is the factory default security setting. NOTE: A valid OEM password allows access to the OEM and user areas of the chip, i.e., the entire memory map, regardless of any user password that may be in place. Once the OEM areas are locked, the user password can provide access and write protection for the user areas. User Password A password is required to access the USER areas of the MIC3001, specifically the non-volatile memory at serial addresses A0h and A2h. A one-byte field, USRPWSET at serial address A2h is used for setting the USER password. USRPWSET is compared to the USRPW field at serial address A2h. If the two fields match, access is allowed to the USER areas of the MIC3001 non-volatile memory at serial addresses A0h and A2h.The USER password is set by writing USRPWSET with the new value. The new password will not take effect until after a power-on reset occurs or a warm reset is performed using the RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. NOTE: A valid OEM password allows access to the OEM and user areas of the chip, i.e., the entire memory map, regardless of any user password that may be in place. Once the OEM areas are locked, the user password can provide access and write protection for the user areas. If a valid OEM password is in place, the user password will have no effect.
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Detailed Register Descriptions
Note: Serial bus addresses shown assume that I2CADR = Axh.
Alarm Threshold Registers
Temperature High Alarm Threshold MSB (TMAXh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 00 = 00h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0C)
Each LSB represents one degree centigrade. This register is to be used in conjunction with TMAXl to yield a sixteenbit temperature value. The value in this register is uncalibrated. The value in TMAXh is compared against TEMPh. Alarm bit Ax is set if TEMPh > TMAXh. Temperature High Alarm Threshold LSB (TMAXh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 01 = 01h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0C)
This register is to be used in conjunction with TMAXh to yield a sixteen-bit temperature value. The value in TMAXh is compared against TEMPh. Alarm bit Ax is set if TMAXh > TEMPh. Since TEMPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. Temperature Low Alarm Threshold MSB (TMINh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 02 = 02h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0C)
Each LSB represents one degree centigrade. This register is to be used in conjunction with TMINl to yield a sixteen-bit temperature value. The value in TMINh is compared against TEMPh. Alarm bit Ax is set if TEMPh < TMINh. Temperature Low Alarm Threshold LSB (TMINl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 03 = 03h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0C)
This register is to be used in conjunction with TMINh to yield a sixteen-bit temperature value. The value in TMINh is compared against TEMPh. Alarm bit Ax is set if TEMPh < TMINh. Since TEMPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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Micrel
Voltage High Alarm Threshold MSB(VMAXh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 08 = 08h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0V)
Each LSB represents 25.6mV. This register is to be used in conjunction with VMAXl to yield a sixteen-bit value. The value in TMINh is compared against VINh. Alarm bit Ax is set if VINh > VMAXh.
Voltage High Alarm Threshold LSB(VMAXl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 09 = 09h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0V)
Each LSB represents 100V. This register is to be used in conjunction with VINh to yield a sixteen-bit value. The value in VMAXh is compared against VINh. Alarm bit Ax is set if VINh > VMAXh. Since VINl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. Voltage Low Alarm Threshold MSB (VMINh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 10 = 0Ah D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0V)
Each LSB represents 25.6mV. This register is to be used in conjunction with VMINl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in VMINh is compared against VINh. Alarm bit Ax is set if VINh0000 0000b = 00h (0V)
Each LSB represents 100V. This register is to be used in conjunction with VINh to yield a sixteen-bit value. The value in VMINh is compared against VINh. Alarm bit Ax is set if VINh < VMINh. Since VINl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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MIC3001
Micrel
Bias Current High Alarm Threshold MSB (IMAXh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 16 = 10h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mA)
This register is to be used in conjunction with IMAXl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in IMAXh is compared against ILDh. Alarm bit Ax is set if ILDh > IMAXh. Bias Current High Alarm Threshold LSB (IMAXl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 17 = 11h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mA)
Each LSB represents 2A. This register is to be used in conjunction with IMAXh to yield a sixteen-bit value. The value in this register is uncalibrated. The value in IMAXh is compared against ILDh. Alarm bit Ax is set if ILDh > IMAXh. Since ILDl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. Bias Current Low Alarm Threshold MSB (IMINh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 18 = 12h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mA)
This register is to be used in conjunction with IMINl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in IMINh is compared against ILDh. Alarm bit Ax is set if ILDh < IMINh. Bias Current Low Alarm Threshold LSB (IMINl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 19 = 13h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mA)
Each LSB represents 2A. This register is to be used in conjunction with IMINh to yield a sixteen-bit value. The value in this register is uncalibrated. The value in IMINh is compared against ILDh. Alarm bit Ax is set if ILDh < IMINh. Since ILDl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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MIC3001
TX Optical Power High Alarm MSB (TXMAXh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 24 = 18h D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 25.6W. This register is to be used in conjunction with TXOPl to yield a sixteen-bit value. The values in TXOPh:TXOPl are in an unsigned binary format. The value in this register is uncalibrated. The value in TXMAXh is compared against TXOPh. Alarm bit Ax is set if TXOPh > TXMAXh. TX Optical Power High Alarm LSB (TXMAXl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 25 = 19h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 0.1W. This register is to be used in conjunction with TXMAXh to yield a sixteen-bit value. The values in TXOPh:TXOPl are in an unsigned binary format. The value in this register is uncalibrated. The value in TXMAXh is compared against TXOPh. Alarm bit Ax is set if TXOPh > TXMAXh. Since TXOPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. TX Optical Power Low Alarm MSB (TXMINh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 26 = 1Ah D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 25.6W. This register is to be used in conjunction with TXMINl to yield a sixteen-bit value. The values in TXMINh:TMINl are in an unsigned binary format. The value in this register is uncalibrated. The value in TXMINh is compared against TXOPh. Alarm bit Ax is set if TXOPh < TXMINh. TX Optical Power Low Alarm LSB (TXMINl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 27 = 1Bh D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 0.1W. This register is to be used in conjunction with TXMINh to yield a sixteen-bit value. The values in TXOPh:TXOPl are in an unsigned binary format. The value in this register is uncalibrated. The value in TXMINh is compared against TXOPh. Alarm bit Ax is set if TXOPh < TXMINh. Since TXOPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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MIC3001
RX Optical Power High Alarm Threshold MSB (RXMAXh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 32 = 20h D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 25.6W. This register is to be used in conjunction with RXMAXl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in RXMAXh is compared against RXOPh. Alarm bit Ax is set if RXOPh > RXMAXh. RX Optical Power High Alarm Threshold LSB (RXMAXl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 33 = 21h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 0.1W. This register is to be used in conjunction with RXMAXh to yield a sixteen-bit value. The values in RXMAXh:RXMAXl are in an unsigned binary format. The value in this register is uncalibrated. The value in RXMAXh is compared against RXOPh. Alarm bit Ax is set if RXOPh > RXMAXh. Since RXOPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. RX Optical Power Low Alarm Threshold MSB (RMINh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 34 = 22h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 25.6W. This register is to be used in conjunction with RXMINl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in RXMINh is compared against RXOPh. Alarm bit Ax is set if RXOPh < RXMINh. RX Optical Power Low Alarm Threshold LSB (RMINl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 35 = 23h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 0.1W. This register is to be used in conjunction with RXMINh to yield a sixteen-bit value. The values in RXMINh:RXMINl are in an unsigned binary format. The value in this register is uncalibrated. The value in RXMINh is compared against RXOPh. Alarm bit Ax is set if RXOPh < RXMINh. Since RXOPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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MIC3001
Micrel
Warning Threshold Registers
Temperature High Warning Threshold MSB (THIGHh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 04 = 04h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0C)
Each LSB represents one degree centigrade. This register is to be used in conjunction with THIGHl to yield a sixteenbit temperature value. The value in this register is uncalibrated. The value in THIGHh is compared against TEMPh. Warning bit Wx is set if TEMPh > THIGHh. Temperature High Warning Threshold LSB (THIGHl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 05 = 05h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0C)
This register is to be used in conjunction with THIGHh to yield a sixteen-bit temperature value. The value in this register is uncalibrated. The value in THIGHh is compared against TEMPh. Warning bit Wx is set if THIGHh > TEMPh. Since TEMPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. Temperature Low Warning Threshold MSB (TLOWh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 06 = 06h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0C)
Each LSB represents one degree centigrade. This register is to be used in conjunction with TLOWl to yield a sixteenbit temperature value. The value in this register is uncalibrated. The value in TLOWh is compared against TEMPh. Warning bit Wx is set if TEMPh < TLOWh. Temperature Low Warning Threshold LSB (TLOWl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 07 = 07h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0C)
This register is to be used in conjunction with TLOWh to yield a sixteen-bit temperature value. The value in this register is uncalibrated. The value in TLOWh is compared against TEMPh. Warning bit Wx is set if TEMPh < TLOWh. Since TEMPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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MIC3001
Voltage High Warning Threshold MSB (VHIGHh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 12 = 0Ch D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h (0V)
Each LSB represents 25.6mV. This register is to be used in conjunction with VHIGHl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in VHIGHh is compared against VINh. Warning bit Wx is set if VINh > VHIGHh. Votage High Warning Threshold LSB (VHIGHl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 13 = 0Dh D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0V)
Each LSB represents 100V. This register is to be used in conjunction with VHIGHh to yield a sixteen-bit value. The value in VHIGHh is compared against VINh. Warning bit Wx is set if VINh > VHIGHh. Since VINl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. Votage Low Warning Threshold MSB (VLOWh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 14 = 0Eh D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0V)
Each LSB represents 25.6mV. This register is to be used in conjunction with VLOWl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in VLOWh is compared against VINh. Warning bit Wx is set if VINh < VLOWhh. Voltage Low Warning Threshold LSB (VLOWl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 15 = 0Fh D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0V)
Each LSB represents 100V. This register is to be used in conjunction with VLOWh to yield a sixteen-bit value. The value in VLOWh is compared against VINh. Warning bit Wx is set if VINh < VLOWh. Since VINl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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MIC3001
Bias Current High Warning Threshold MSB (IHIGHh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 20= 14h D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h (0mA)
This register is to be used in conjunction with IHIGHl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in IHIGHh is compared against ILDh. Warning bit Wx is set if ILDh > IHIGHh. Bias Current High Warning Threshold LSB (IHIGHl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 21= 15h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mA)
Each LSB represents 2A. This register is to be used in conjunction with IHIGHh to yield a sixteen-bit value. The value in this register is uncalibrated. The value in IHIGHh is compared against ILDh. Warning bit Wx is set if ILDh > IHIGHh. Since ILDl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. Bias Current Low Warning Threshold MSB (ILOWh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 22= 16h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mA)
This register is to be used in conjunction with ILOWl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in ILOWh is compared against ILDh. Warning bit Wx is set if ILDh < ILOWh. Bias Current Low Warning Threshold LSB (ILOWl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 23= 17h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mA)
Each LSB represents 2A. This register is to be used in conjunction with ILOWh to yield a sixteen-bit value. The value in this register is uncalibrated. The value in ILOWh is compared against ILDh. Warning bit Wx is set if ILDh < ILOWh. Since ILDl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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MIC3001
TX Optical Power High Warning MSB (TXHIGHh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 28= 1Ch D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 25.6W. This register is to be used in conjunction with TXHIGHl to yield a sixteen-bit value. The values in TXHIGHh:TXHIGHl are in an unsigned binary format. The value in this register is uncalibrated. The value in TXHIGHh is compared against TXOPh. Warning bit Wx is set if TXOPh > TXHIGHh. TX Optical Power High Warning LSB (TXHIGHl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 29= 1Dh D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 0.1W. This register is to be used in conjunction with TXHIGHh to yield a sixteen-bit value. The values in TXHIGHh:TXHIGHl are in an unsigned binary format. The value in this register is uncalibrated. The value in TXHIGHh is compared against TXOPh. Warning bit Wx is set if TXOPh > TXHIGHh. Since TXOPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning b. TX Optical Power Low Warning MSB (TLOWh) D[7] read/write Default Value Serial Address Byte Address D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0000 0000b = 00h (0mW) A2h = 1010001b 30 = 1Eh
Each LSB represents 25.6W. This register is to be used in conjunction with TXLOWl to yield a sixteen-bit value. The values in TXLOWh:TLOWl are in an unsigned binary format. The value in this register is uncalibrated. The value in TXLOWh is compared against TXOPh. Warning bit Wx is set if TXOPh < TXLOWh. TX Optical Power Low Warning LSB (TLOWl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 31 = 1Fh D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 0.1W. This register is to be used in conjunction with TXLOWh to yield a sixteen-bit value. The values in TXLOWh:TXLOWl are in an unsigned binary format. The value in this register is uncalibrated. The value in TXLOWh is compared against TXOPh. Warning bit Wx is set if TXOPh < TXLOWh. Since TXOPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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MIC3001
RX Optical Power High Warning Threshold MSB (RXHIGHh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 36 = 24h D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 25.6W. This register is to be used in conjunction with RXHIGHl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in RXHIGHh is compared against RXOPh. Warning bit Wx is set if RXOPh > RXHIGHh. RX Optical Power High Warning Threshold LSB (RXHIGHl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 37 = 25h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 0.1W. This register is to be used in conjunction with RXHIGHh to yield a sixteen-bit value. The values in RXHIGHh:RXHIGHl are in an unsigned binary format. The value in this register is uncalibrated. The value in RXHIGHh is compared against RXOPh. Warning bit Wx is set if RXOPh > RXHIGHh. Since RXOPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. RX Optical Power Low Warning Threshold MSB (RXLOWh) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 38 = 26h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 25.6W. This register is to be used in conjunction with RXLOWl to yield a sixteen-bit value. The value in this register is uncalibrated. The value in RXLOWh is compared against RXOPh. Warning bit Wx is set if RXOPh < RXLOWh. RX Optical Power Low Warning Threshold LSB (RXLOWl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 39 = 27h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h (0mW)
Each LSB represents 0.1W. This register is to be used in conjunction with RXLOWh to yield a sixteen-bit value. The values in RXLOWh:RXLOWl are in an unsigned binary format. The value in this register is uncalibrated. The value in RXLOWh is compared against RXOPh. Warning bit Wx is set if RXOPh < RXLOWh. Since RXOPl is always zero, it is recommended that this register always be programmed to zero. This register is provided for compliance with SFF8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
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MIC3001
Checksum (CHKSUM) Checksum of bytes 0 - 94 at serial address A2h D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A2h = 1010001b 95 = 5Fh D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h (0C)
This register is provided for compliance with SFF-8472. It is implemented as general-purpose non-volatile memory. Read/write access is possible whenever a valid OEM password has been entered. CHKSUM is read-only in USER mode.
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MIC3001
Micrel
ADC Result Registers
Temperature Result MSB (TEMPh) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 96 = 60h D[3] read-only D[2] read-only D[1] read-only D[0] read-only
0000 0000b = 00h (0C)(1)
Each LSB represents one degree centigrade. This register is to be used in conjunction with TEMPl to yield a sixteenbit temperature value. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. Temperature Result LSB (TEMPl) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 97 = 61h D[3] read-only D[2] read-only D[1] read-only D[0] read-only
0000 0000b = 00h (0C)
This register is to be used in conjunction with TEMPh to yield a sixteen-bit temperature value. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. In the MIC3001, this register will always return zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. Voltage MSB (VINh) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 98 = 62h D[3] read-only D[2] read-only D[1] read-only D[0] read-only
0000 0000b = 00h (0V)(2)
Each LSB represents 25.6mV. This register is to be used in conjunction with VINl to yield a sixteen-bit value. The values in VINh:VlNl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. Voltage LSB (VINl) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 99 = 63h D[3] read-only D[2] read-only D[1] read-only D[0] read-only
0000 0000b = 00h (0V)
Each LSB represents 100V. This register is to be used in conjunction with VINh to yield a sixteen-bit value. The values in VINh:VINl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. In the MIC3001, this register will always return zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits.
Notes: 1. TEMPh will contain measured temperature data after the completion of one conversion. 2. VINh will contain measured data after one A/D conversion cycle.
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Laser Diode Bias Current MSB (ILDh) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 100 = 64h D[3] read-only D[2] read-only D[1] read-only
Micrel
D[0] read-only
0000 0000b = 00h (0mA)(3)
This register is to be used in conjunction with ILDl to yield a sixteen-bit value. The values in ILDh:ILDl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration sections.
Laser Diode Bias Current LSB (ILDl) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 101 = 65h D[3] read-only D[2] read-only D[1] read-only D[0] read-only
0000 0000b = 00h (0mA)
Each LSB represents 2A. This register is to be used in conjunction with ILDh to yield a sixteen-bit value. The values in ILDh:ILDl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. In the MIC3001, this register will always return zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. Transmitted Optical Power MSB (TXOPh)(4) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 102 = 66h D[3] read-only D[2] read-only D[1] read-only D[0] read-only
0000 0000b = 00h (0mW)(5)
Each LSB represents 25.6W. This register is to be used in conjunction with TXOPl to yield a sixteen-bit value. The values in TXOPh:TXOPl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. Transmitted Optical Power LSB (TXOPl) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 103 = 67h D[3] read-only D[2] read-only D[1] read-only D[0] read-only
0000 0000b = 00h (0mW)
Each LSB represents 0.1W. This register is to be used in conjunction with TXOPh to yield a sixteen-bit value. The values in TXOPh:TXOPl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. In the MIC3001, this register will always return zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bitsection.
Notes: 3. ILDh will contain measured data after one A/D conversion cycle. 4. The scale factor corresponding to the sense resistor used must be set in the configuration register. 5. TXOPh will contain measured data after one A/D conversion cycle.
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Received Optical Power MSB (RXOPh) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 104 = 68h D[3] read-only D[2] read-only D[1] read-only
Micrel
D[0] read-only
0000 0000b = 00h (0mW)(6)
Each LSB represents 25.6W. This register is to be used in conjunction with RXOPl to yield a sixteen-bit value. The values in RXOPh:RXOPl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. Received Optical Power LSB (RXOPl) D[7] read-only Default Value Serial Address Byte Address D[6] read-only D[5] read-only D[4] read-only A2h = 1010001b 105 = 69h D[3] read-only D[2] read-only D[1] read-only D[0] read-only
0000 0000b = 00h (0mW)(6)
Each LSB represents 0.1W. This register is to be used in conjunction with RXOPh to yield a sixteen-bit value. The values in RXOPh:RXOPl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the coefficients provided. See the External Calibration section. In the MIC3001, this register will always return zero. This register is provided for compliance with SFF-8472. It is not used by the MIC3001 when doing threshold comparisons and setting alarm or warning bits. Control and Status (CNTRL) D[7] TXDIS read only Default Value Serial Address Byte Address D[6] STXDIS read/write D[5] reserved D[4] RSEL read/write A2h = 1010001b 110 = 6Eh
Function TXDIS STXDIS D[5] RSEL SRSEL TXFLT LOS POR Reflects the state of the TXDISABLE pin Soft transmit disable Reserved Reflects the state of the RSEL pin Soft rate select Reflects the state of the TXFAULT pin Loss of signal. Reflects the state of the LOS pin MIC3001 power-on status Operation 1 = disabled, 0 = enabled, read only. 1 = disabled; 0 = enabled. Reserved - always write as zero. 1 = high; 0 = low. 1 = high (2Gbps); 0 = low (1Gbps). 1 = high (fault); 0 = low (no fault). 1 = high (loss of signal); 0 = low (no loss of signal). 0 = POR complete, analog data ready; 1 = POR in progress.
D[3] SRSEL read/write
D[2] XFLT read only
D[1] LOS read only
D[0] POR read only
0000 0000b = 00h
Bit(s) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Notes:
6. RXOPh will contain measured data after one A/D conversion cycle.
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Micrel
Alarm Flags
Alarm Register 0 (ALARM0) D[7] A7 read-only Default Value Serial Address Byte Address D[6] A6 read-only D[5] A5 read-only D[4] A4 read-only A2h = 1010001b 112 = 70h D[3] A3 read-only D[2] A2 read-only D[1] A1 read-only D[0] A0 read-only
0000 0000b = 00h (no events pending)
The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending on the results.
Bit(s) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A7 A6 A5 A4 A3 A2 A1 A0 Function High temperature alarm, TEMPh > TMAXh. Low temperature alarm, TEMPh < TMINh. High voltage alarm, VINh > VMAXh. Low voltage alarm, VINh < VMINh. High laser diode bias alarm, IBIASh > IMAXh. Low laser diode bias alarm, IBIASh < IMINh. High transmit optical power alarm, TXOPh > TXMAXh. Low transmit optical power alarm, TXOPh < TXMINh. Operation 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK.
Alarm Register 1 (ALARM1) D[7] A15 read-only Default Value Serial Address Byte Address D[6] A14 read-only D[5] reserved D[4] reserved A2h = 1010001b 113 = 71h D[3] reserved D[2] reserved D[1] reserved D[0] reserved
0000 0000b = 00h (no events pending)
The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending on the results.
Bit(s) D[7] D[6] D[5:0] A15 A14 Function High received power (overload) alarm, RXOPh > RXMAXh. Low received power (LOS) alarm, RXOPh < RXMINh. Reserved Operation 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. Reserved - always write as zero.
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Micrel
Warning Flags
Warning Register 0 (WARN0) D[7] W7 read-only Default Value Serial Address Byte Address D[6] W6 read-only D[5] W5 read-only D[4] W4 read-only A2h = 1010001b 116 = 74h D[3] W3 read-only D[2] W2 read-only D[1] W1 read-only D[0] W0 read-only
0000 0000b = 00h (no events pending)
The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending on the results.
Bit(s) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] W7 W6 W5 W4 W3 W2 W1 W0 Function High temperature warning, TEMPh > THIGHh. Low temperature warning, TEMPh < TLOWh. High voltage warning, VINh > VHIGHh. Low voltage warning, VINh < VLOWh. High laser diode bias warning, IBIASh > IHIGHh. Low laser diode bias warning, IBIASh < ILOWh. High transmit optical power warning, TXOPh > TXHIGHh. Low transmit optical power warning, TXOPh < TXLOWh. Operation 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK. 1 = condition exists, 0 = normal/OK.
Warning Register 1 (WARN1) D[7] W15 read-only Default Value Serial Address Byte Address D[6] W14 read-only D[5] read-only D[4] read-only A2h = 1010001b 117 = 75h D[3] read-only D[2] read-only D[1] read-only D[0] read-only
0000 0000b = 00h (no events pending)
The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending on the results.
Bit(s) D[7] D[6] D[5:0] W15 W14 Function Received power high warning, RXOPh > RXHIGHh. Operation 1 = condition exists, 0 = normal/OK.
Received power low warning, RXOPh < RXMINh. 1 = condition exists, 0 = normal/OK. Reserved Reserved - always write as zero.
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OEM Password Entry (OEMPW) D[7] Read/write Default Value Serial Address Byte Address D[6] Read/write D[5] Read/write D[4] Read/write D[3] Read/write D[2] Read/write D[1] Read/write
Micrel
D[0] Read/write
0000 0000b = 00h (reset to zero at power-on) A2h = 1010001b 120 - 123 = 78h - 7Bh (MSB is 7Bh)
This four-byte field is for entry of the password required to access the OEM area of the MIC3001's memory and registers. A valid OEM password will also permit access to the user areas of memory. The byte at address 123 (7Bh) is the most significant byte. This field is compared to the four-byte OEMPWSET field at serial address A6h, bytes 12 to 15. If the two fields match, access is allowed to the OEM areas of the MIC3001 non-volatile memory at serial addresses A4h and A6h. The OEM password is set by writing the new value into OEMPWSET. The password comparison is performed following the write to the MSB, address 7Bh. This byte must be written last! A four-byte burst-write sequence to address 78h may be used as this will result in the MSB being written last. The new password will not take effect until after a power-on reset occurs or a warm reset is performed using the RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. This field is reset to all zeros at power on. Any values written to these locations will be readable by the host regardless of the locked/unlocked status of the device. If OEMPWSET is set to zero (00000000h), the MIC3001 will remain unlocked regardless of the contents of the OEMPW field. This is the factory default security setting. BYTE 3 2 1 0 Weight OEM Password Entry, Most Significant Byte (Address = 7Bh) OEM Password Entry, 2nd Most Significant Byte (Address = 7Ah) OEM Password Entry, 2nd Least Significant Byte (Address = 79h) OEM Password Entry, Least Significant Byte (Address = 78h) USER Password Setting (USRPWSET) D[7] Read/write Default Value Serial Address Byte Address D[6] Read/write D[5] Read/write D[4] Read/write D[3] Read/write D[2] Read/write D[1] Read/write D[0] Read/write
0000 0000b = 00h A2h = 1010001b 250 = FAh
This register is for setting the password required to access the USER area of the MIC3001's memory and registers. This field is compared to the USRPW field at serial address A2h, byte 251. If the two fields match, access is allowed to the USER areas of the MIC3001 non-volatile memory at serial addresses A0h and A2h. If a valid USER password has not been entered, writes to the serial ID fields, USRCTRL, and the user scratchpad areas of A0h and A2h will not be allowed, and USRPWSET will be unreadable (returns all zeroes). A USER password is set by writing the new value into USRPWSET. The new password will not take effect until after a power-on reset occurs or a warm reset is performed using the RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. This register is non-volatile and will be maintained through power and reset cycles. A valid USER or OEM password is required for access to this register. Otherwise, this register will read as 00h. Note: a valid OEM password overrides the USER password setting. If a valid OEM password is currently in place, the user password will have no effect.
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USER Password (USRPW) D[7] Read/write Default Value Serial Address Byte Address D[6] Read/write D[5] Read/write D[4] Read/write D[3] Read/write D[2] Read/write D[1] Read/write
Micrel
D[0] Read/write
0000 0000b = 00h A2h = 1010001b 251 = FBh
USER passwords are entered in this field. This field is compared to the USRPWSET field at serial address A2h, byte 250. If the two fields match, access is allowed to the USER areas of the MIC3001 non-volatile memory at serial addresses A0h and A2h. If a valid USER password has not been entered, writes to the serial ID fields and user scratchpad areas of A0h and A2h will not be allowed and USRPWSET will be unreadable (returns all zeroes). Power-On Hours MSB (POHh) D[7] read-only Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write
POH Fault Flag (POHFLT) 0000 0000b = 00h A2h = 1010001b 252 = FCh
The lower seven bits of this register contain the most-significant bits of the 15-bit power-on hours measurement. POHFLT is an error flag. The value in this register should be combined with the Power-on Hours, Low Byte, POHl, to yield the complete result. If POHFLT is set, the power-on hour meter data has been corrupted and should be ignored. It is recommended that a two-byte (or more) sequential read operation be performed on POHh and POHl to insure coherency between the two registers. This register is non-volatile and will be maintained through power and reset cycle.
Bit(s) D[7] D[6:0] Function Power-on hours fault flag Power-on hours, high byte Operation 1 = fault; 0 = no fault. Non-volatile.
Power-On Hours LSB (POHl) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write
POH Fault Flag (POHFLT) 0000 0000b = 00h A2h = 1010001b 253 = FDh
This register contains the least-significant eight bits of the 15-bit power-on hours measurement. The value in this register should be combined with the Power-on Hours, High Byte, POHh, to yield the complete result. If POHFLT is set, the power-on hour meter data has been corrupted and should be ignored. It is recommended that a two-byte (or more) sequential read operation be performed on POHh and POHl to insure coherency between the two registers. This register is non-volatile and will be maintained through power and reset cycles.
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Data Ready Flags (DATARDY) D[7] TRDY read only Default Value Serial Address Byte Address D[6] VRDY read only D[5] IRDY read only D[4] TXRDY read only A2h = 1010001b 254 = FEh D[3] RXRDY read only D[2] reserved D[1] reserved
Micrel
D[0] reserved
0000 0000b = 00h
When the A/D conversion for a given parameter is completed and the results available to the host, the corresponding data ready flag will be set. The flag will be cleared when the host reads the corresponding result register.
Bit(s) D[7] D[6] D[5] D[4] D[3] D[2:0] TRDY VRDY IRDY TXRDY RXRDY Function Temperature data ready flag Voltage data ready flag Bias current data ready flag Transmit power data ready flag Receive power data ready flag Reserved Operation 0 = old data; 1 = new data ready 0 = old data; 1 = new data ready 0 = old data; 1 = new data ready 0 = old data; 1 = new data ready 0 = old data; 1 = new data ready Reserved
USER Control Register (USRCTL) D[7] reserved Default Value Serial Address Byte Address D[6] PORM read/write D[5] PORS read only D[4] IE read/write A2h = 1010001b 255 = FFh D[3] APCSEL read/write D[2] read/write D[1] reserved D[0] reserved
0010 0000b = 20h
This register provides for control of the nominal APC setpoint and management of interrupts by the end-user. APCSEL[1:0] select which of the APC setpoint registers, APCSET0, APCSET1, or APCSET2 are used as the nominal automatic power control setpoint. IE must be set for any interrupts to occur. If PORM is set, the power-on event will generate an interrupt and warm resets using RST will not generate a POR interrupt. When a power-on interrupt occurs, assuming PORM=1, PORS will be set. PORS will be cleared and the interrupt output de-asserted when USRCTL is read by the host. If IE is set while / INT is asserted, /INT will be de-asserted. The host must still clear the various status flags by reading them. If PORM is set following the setting of PORS, PORS will remain set, and /INT will not be de-asserted, until USRCTL is read by the host. PORM, IE, and APCSEL are non-volatile and will be maintained through power and reset cycles. A valid USER password is required for access to this register.
Bit D[7] D[6] D[5] D[4] D[3:2] D[1:0] PORM PORS IE APCSEL Function Reserved Power-on interrupt mask Power-on interrupt flag Global interrupt enable Selects APC setpoint register Reserved Operation Always write as zero; reads undefined. 1 = POR interrupts enabled; 0 = disabled; read/write; non-volatile. 1 = POR interrupt occurred; 0 = no POR interrupt; read-only. 1 = enabled; 0 = disabled; read/write; non-volatile. 00 = APCSET0, 01 = APCSET1, 10 = APCSET2; 11 = reserved; read/write; non-volatile. Always write as zero; reads undefined.
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OEM Configuration Register 0 (OEMCFG0) D[7] RST write only Default Value Serial Address Byte Address D[6] ZONE read/write D[5] DFLT read only D[4] OE reserved A6h = 1010011b 00 = 00h D[3] MODREF reserved D[2] VAUX[2] read/write D[1] VAUX[1] read/write
Micrel
D[0] VAUX[0] read/write
0000 0000b = 00h
A write to OEMCFG0 will result in any A/D conversion in progress being aborted and the result discarded. The A/D will begin a new conversion sequence once the write operation is complete. All bits in OEMCFG0 are non-volatile except DFLT and RST. A valid OEM password is required for access to this register.
Bit(s) D[7] D[6] D[5] D[4] D[3] D[2:0] RST ZONE DFLT OE MODREF VAUX[2:0] Selects temperature zone. Diode fault flag. Output enable for SHDN, VMOD, and VBIAS. Selects whether VMOD is referenced to ground or VDD. Selects the voltage reported in VINh:VINl. Function Operation 0 = no action; 1 = reset; write-only. 0 = internal; 1 = external; non-volatile. 1 = diode fault; 0 = OK. 1 = enabled; 0 = hi-Z; non-volatile. 1 = VDD; 0 = GND; non-volatile. 000 = VIN; 001 = VDDA; 010 = VBIAS; 011 = VMOD; 100 = APCDAC; 101 = MODDAC; 110 = FLTDAC; non-volatile
OEM Configuration Register 1 (OEMCFG1) D[7] INV read/write Default Value Serial Address Byte Address D[6] GAIN read/write D[5] BIASREF read/write D[4] RFB[2] read/write A6h = 1010011b 1 = 01h D[3] RFB[1] read/write D[2] RFB[0] read/write D[1] SRCE read/write D[0] SPOL read/write
0000 0000b = 00h
A write to OEMCFG1 will result in any A/D conversion in progress being aborted and the result discarded. The A/D will begin a new conversion sequence once the write operation is complete. All bits in OEMCFG1 are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register.
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Bit(s) D[7] INV Function Operation
Micrel
Inverts the APC op-amp inputs. When set to "0" 0 = emitter follower (no inversion); the BIAS DAC output is connected to the "+" 1 = common emitter (inverted); read/write; input and FB is connected to the "-" input of the non-volatile. op amp. Set to "0" to use the ADC feedback loop. Sets the feedback voltage range by changing the APCDAC output swing; 0-VREF for optical feedback, 0-VREF/4 for electrical feedback. Selects whether FB and VMPD are referenced to ground or VDD and selects feedback resistor termination voltage (VDDA or GNDA). Selects internal feedback resistance. (Resistors will be terminated to VDDA or GNDA according to BIASREF.) 1 = VREF/4 full scale; 0 = VREF full scale; read/write ;non-volatile. 1 = VDD; 0 = GND; read/write; non-volatile.
D[6]
GAIN
D[5]
BIASREF
D[4:2]
RFB[2:0]
000 = ; 001 = 800, 010 = 1.6k, 011 = 3.2k, 100 = 6.4k, 101 = 12.8k, 110 = 25.6k, 111 = 51.2k; read/write; non-volatile. 1 = source (NPN), 0 = sink (PNP); read/write; non-volatile. 1 = high; 0 = low; read/write; non-volatile.
D[1] D[0]
SRCE SPOL
VBIAS source vs. sink drive. Polarity of shutdown output, SHDN, when active.
OEM Configuration Register 2 (OEMCFG2) D[7] I2CADR[3] read/write Default Value Serial Address Byte Address D[6] I2CADR[2] read/write D[5] I2CADR[1] read/write D[4] I2CADR[0] read/write D[3] LUTOFF read/write D[2] LUTOFF read/write D[1] LUTOFF read/write D[0] LUTOFF read/write
1010 xxxxb = xxh (slave address = 1010xxxb) A6h = 1010011b 2 = 02h
CAUTION: Changes to I2CADR take effect immediately! Any accesses following a write to I2CADR must be to the newly programmed serial bus address. A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles.
Bit(s) D[7:4] D[3:0] I2CADR[3:0] LUTOFF Function Upper four MSBs of the serial bus slave address; writes take effect immediately. LUT offset. LUTOFF is added to the result of the digital temperature sensor to derive the table index; writes take effect after reset. Operation Read/write; non-volatile. Read/write; non-volatile.
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APC Setpoint 0 (APCSET0) Automatic power control setpoint (unsigned binary) used when APCSEL[1:0] = 00 D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 3 = 03h D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h
When A.P.C. is on, i.e., the APCCAL bit in OEMCAL0 is set, the value in APCSETx is added to the signed value taken from the A.P.C. look-up table and loaded into the VBIAS DAC. When A.P.C. is off, the value in APCSET is loaded directly into the VBIAS DAC, bypassing the look-up table entirely. In either case, the VBIAS DAC setting is reported in the VBIAS register. The APCCFG bits determine the DAC's response to higher or lower numeric values. A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. APC Setpoint 1 (APCSET1) Automatic power control setpoint (unsigned binary) used when APCSEL[1:0] = 01 D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 4 = 04h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h
When A.P.C. is on, i.e., the APCCAL bit in OEMCAL0 is set, the value in APCSETx is added to the signed value taken from the A.P.C. look-up table and loaded into the VBIAS DAC. When A.P.C. is off, the value in APCSET is loaded directly into the VBIAS DAC, bypassing the look-up table entirely. In either case, the VBIAS DAC setting is reported in the VBIAS register. The APCCFG bits determine the DAC's response to higher or lower numeric values. This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register. APC Setpoint 2 (APCSET2) Automatic power control setpoint (unsigned binary) used when APCSEL[1:0] = 10 D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 5 = 05h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h
When A.P.C. is on, i.e., the APCCAL bit in OEMCAL0 is set, the value in APCSETx is added to the signed value taken from the A.P.C. look-up table and loaded into the VBIAS DAC. When A.P.C. is off, the value in APCSET is loaded directly into the VBIAS DAC, bypassing the look-up table entirely. In either case, the VBIAS DAC setting is reported in the VBIAS register. The APCCFG bits determine the DAC's response to higher or lower numeric values. This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register.
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Modulation DAC Setting (MODSET) Nominal VMOD setpoint D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 6 = 06h D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h
When A.P.C. is on, the value corresponding to the current temperature is taken from the MODLUT look-up table, added to MODSET and loaded into the VMOD DAC. This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register. IBIAS Fault Threshold (IBFLT) Bias current fault threshold D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 7 = 07h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. A fault is generated if the bias current is higher than IBFLT value set in this register. Transmit Power Fault Threshold (TXFLT) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 8 = 08h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. A fault is generated if the Transmit power is higher than TXFLT value set in this register. Loss-Of-Signal Threshold (LOSFLT) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 9 = 09h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. A fault is generated if the received power is lower than LOSFLT value set in this register.
Bit D[7:0] Function Receive loss-of-signal threshold Operation Read/write; non-volatile.
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Fault Suppression Timer (FLTTMR) Fault suppression interval in increments of 0.5ms D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 10 = 0Ah D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h
Saturation faults are suppressed for a time, tFLTTMR, following laser turn-on. This avoids nuisance tripping while the APC loop starts up. The length of this interval is (FLTTMRx0.5ms), typical. A value of zero will result in no fault suppression. A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. Fault Mask (FLTMSK) D[7] OEMIM read/write Default Value Serial Address Byte Address D[6] POHE read/write D[5] reserved D[4] reserved A6h = 1010011b 11 = 0Bh D[3] SATMSK read/write D[2] TXMSK read/write D[1] IAMSK read/write D[0] DFMSK read/write
0000 0000b = 00h
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles.
Bit D[7] D[6] D[5:4] D[3] D[2] D[1] D[0] OEMIM POHE D[5:4] SATMSK TXMSK IAMSK DFMSK Function OEM interrupt mask bit OEM Power-on Hour Meter enable bit Reserved APC saturation fault mask bit High TX optical power fault mask bit Bias current high alarm mask bit Diode fault mask bit Operation 1 = masked; 0 = enabled; Read/write; non-volatile. 1 = enabled; 0 = disabled; Read/write; non-volatile. Always write as zero; reads undefined. 1 = masked; 0 = enabled; Read/write; non-volatile. 1 = masked; 0 = enabled; Read/write; non-volatile. 1 = masked; 0 = enabled; Read/write; non-volatile. 1 = masked; 0 = enabled; Read/write; non-volatile.
OEM Password Setting (OEMPWSET) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 12 - 15 = 0Fh - 0Fh; 0Ch = MSB D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h
This four-byte field is the password required for access to the OEM area of the MIC3001's memory and registers. The byte at address 250 (FAh) is the most significant byte. This field is compared to the four-byte OEMPW field at serial address A2h, byte 120 to 123. If the two fields match, access is allowed to the OEM areas of the MIC3001 non-volatile memory at serial addresses A4h and A6h. The OEM password may be set by writing the new value into OEMPWSET. The new password will not take effect until after a power-on reset occurs or a warm reset is performed using the RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register.
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BYTE 3 2 1 0 OEM Password, Most Significant Byte OEM Password, 2nd Most Significant Byte OEM Password, 2nd Least Significant Byte OEM Password, Least Significant Byte Weight
Micrel
OEM Calibration 0 (OEMCAL0) D[7] reserved Default Value Serial Address Byte Address D[6] FLTDIS read/write D[5] FSPIN read/write D[4] WRINH read/write A6h = 1010011b 16 = 10h D[3] APCCAL read/write D[2] FRCINT read/write D[1] FRCTXF read/write D[0] FRCLOS read/write
0000 0000b = 00h
A valid OEM password is required for access to this register.
Bit D[7] D[6] D[5] FLTDIS FSPIN Function Reserved Fault comparator disable; inhibits output of fault comparators when set. Fault comparator "spin-on-channel" mode select; do not enable ADC and FC spin-on-channel modes simultaneously. Inhibit NVRAM write cycles. Selects APC calibration mode - DACs may be controlled directly. Forces the assertion of /INT Forces the assertion of TXFAULT Forces the assertion of RXLOS Operation Always write as zero; reads undefined. 0 = faults enabled; 1 = disabled; Read/write. 0 = normal operation; 1 = spin on channel; Read/write. 0 = normal operation; 1 = inhibit writes; Read/write. 0 = normal mode; 1 = calibration mode; Read/write. 0 = normal operation; 1 = asserted; Read/write. 0 = normal operation; 1 = asserted; Read/write. 0 = normal operation; 1 = asserted; Read/write.
D[4] D[3] D[2] D[1] D[0]
WRINH APCCAL FRCINT FRCTXF FRCLOS
OEM Calibration 1 (OEMCAL1) D[7] reserved Default Value Serial Address Byte Address D[6] ADSTP read/write D[5] ADIDL read/write D[4] 1SHOT read/write A6h = 1010011b 17 = 11h D[3] ADSPIN read/write D[2] SPIN[2] read/write D[1] SPIN[1] read/write D[0] SPIN[0] read/write
0000 0000b = 00h
A valid OEM password is required for access to this register.
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Bit D[7] D[6] D[5] D[4] D[3] ADSTP ADIDL 1SHOT ADSPIN Function Reserved Stop ADC Halts the analog to digital converter ADC idle flag Triggers one-shot A/D conversion cycle Selects ADC spin-on-channel mode; do not enable ADC and FC spin-on-channel modes simultaneously Operation Always write as zero; reads undefined. 0 = normal operation; 1 = stopped; Read/write. 0 = busy; 1 = idle; Read/write. 0 = normal operation; 1 = one-shot; Read/write. 0 = normal operation; 1 = spin-on-channel; Read/write.
Micrel
D[2], D[1], D[0]
SPIN[2:0]
ADC and fault comparator (FC) channel select for ADC: 000 = temperature; 001 = voltage; 010 = VILD; spin-on-channel mode; do not enable ADC and 011 = VMPD; 100 = VRX; FC: 001 = VILD; FC spin-on-channel modes simultaneously 001 = VMPD; 010 = VRX; Read/write.
Look-Up Table Index (LUTINDX) Look-up table index as determined by temperature compensation logic D[7] read/write Default Value Serial Address Byte Address
( ) T INDEX = AVG + LUTOFF 2
D[6] read/write
D[5] read/write
D[4] read/write
D[3] read/write
D[2] read/write
D[1] read/write
D[0] read/write
0000 0000b = 00h A6h = 1010011b 18 = 12h
The look-up table index is derived from the current temperature measurement and LUTOFF as follows: where TAVG(n) is the current average temperature. This register allows the current table
index to be read by the host. The table base address must be added to LUTINDX to form a complete table index in physical memory. A valid OEM password is required for access to this register. Otherwise, reads are undefined. OEM Configuration 3 (OEMCFG3) D[7] LUTSEL read/write Default Value Serial Address Byte Address D[6] TXFPOL read/write D[5] GPOD read/write D[4] GPOM read/write A6h = 1010011b 19 = 13h D[3] GPOC read/write D[2] TXFIN read/write D[1] LOSDIS read/write D[0] INTCAL read/write
0000 1000b = 08h
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register. GPOD and GPOC are ignored when GPOM = 0. TXFPOL is ignored if TXFIN = 0.
Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] LUTSEL TXFPOL GPOD GPOM GPOC TXFIN LOSDIS INTCAL Function RX power look-up table input selection bit TXFIN active polarity select; a fault is indicated when TXFIN = TXFPOL GPO output drive GPO/RSOUT mode select GPO output control TXFIN mode select RXLOS comparator disable Calibration mode select Operation 1 = RX power; 0 = temperature; read/write; ignored if INTCAL = 0. 0 = active-low; 1 = active-high; read/write; ignored if TXFIN = 0. 0 = open drain; 1 = push-pull; read/write; ignored if GPOM = 0. 0 = RSOUT; 1 = GPO; read/write. 0 = low; 1 = high; read/write; ignored if GPOM = 0. 0 = SHDN; 1 = TXFIN; read/write. 0 = enabled; 1 = disabled; read/write. 0 = external calibration; 1 = internal calibration; read/write.
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BIAS DAC Setting (APCDAC) Current VBIAS setting D[7] read only Default Value Serial Address Byte Address D[6] read only D[5] read only D[4] read only A6h = 1010011b 20 = 14h D[3] read only D[2] read only D[1] read only
Micrel
D[0] read only
0000 0000b = 00h
This register reflects (reads back) the value set in the APC register (APCSET0, APCSET1, or APCSET2 whichever is selected). A valid OEM password is required for access to this register. Modulation DAC Setting (MODDAC) Current VMOD setting D[7] read only Default Value Serial Address Byte Address D[6] read only D[5] read only D[4] read only A6h = 1010011b 21 = 15h D[3] read only D[2] read only D[1] read only D[0] read only
0000 0000b = 00h
This register reflects (reads back) the value set in the MODSET register. A valid OEM password is required for access to this register. OEM Readback Register (OEMRD) D[7] reserved Default Value Serial Address Byte Address D[6] reserved D[5] reserved D[4] INT read only A6h = 1010011b 22 = 16h D[3] APCSAT read only D[2] IBFLT read only D[1] TXFLT read only D[0] RSOUT read only
0000 0000b = 00h
This register reflects (reads back) the status of the bits corresponding to the parameters defined below. A valid OEM password is required for access to this register. Otherwise, reads are undefined and writes are ignored.
Bit D[7:5] D[4] D[3] D[2] D[1] D[0] INT APCSAT IBFLT TXFLT RSOUT Function Reserved Mirrors state of /INT but active-high; not state of physical pin! APC saturation fault comparator output state State of IBIAS over-current fault comparator output State of transmit power fault comparator output State of the rate select output pin, RSOUT Operation Always write as zero; reads undefined. 1 = interrupt; 0 = no interrupt. 1 = fault; 0 = normal operation. 1 = fault; 0 = normal operation; read-only. 1 = fault; 0 = normal operation; read-only. 1 = high; 0 = low; Read-only..
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Signal Detect Threshold (LOSFLTn) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 23 = 17h D[3] read/write D[2] read/write D[1] read/write
Micrel
D[0] read/write
0000 0000b = 00h
This register works in conjunction with the LOSFLT register to control the operation of the loss of signal comparator. The comparator's output, RXLOS, is asserted when the input on VRX falls below the level in LOSFLT. The output will then be deasserted when the VRX signal rises above LOSFLTn. The input signal is subject to scaling by the RXPOT. If the LOS comparator is disabled, i.e., LOSDIS = 1, this register is ignored. A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. RX EEPOT Tap Selection (RXPOT) D[7] reserved Default Value Serial Address Byte Address D[6] reserved D[5] reserved D[4] read/write A6h = 1010011b 24 = 18h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers.
Bit(s) D[7:5] D[4:0] Function Reserved. RXPOT tap selection: 00000 = No divider action; POT disconnected 00001 = 31/32 00010 = 30/32 * * * 11110 = 2/32 11111 = 1/32 Operation Reserved. Always write as zero; reads undefined. Read/write; non-volatile.
OEM Configuration 4 (OEMCFG4) D[7] Reserved Default Value Serial Address Byte Address D[6] Reserved D[5] Reserved D[4] Reserved D[3] Read/write D[2] Read/write D[1] Read/write D[0] Read/write
0000 0000b = 00h A6h = 1010011b 25 = 19h
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers.
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Bit(s) D[7:4] ISTART[3:0] Function Reserved. ISTART current level selection: 0000 = No ISTART current 0001 - 1111 = 0.375mA x ISTART[3:0] ISTART is used to speed up the laser start-up after a fault accures. The charging current of the compensation cap starts from ISTART instead of ramping up from 0. Operation Reserved. Always write as zero; reads undefined. Read/write; non-volatile.
Micrel
Power-On Hour Meter Data (POHDATA) D[7] read/write Default Value Serial Address Byte Address D[6] read/write D[5] read/write D[4] read/write A6h = 1010011b 32-39 = 20h - 27h D[3] read/write D[2] read/write D[1] read/write D[0] read/write
0000 0000b = 00h
These registers are used for backing up the POH result during power cycles. At power-up, the POH meter selects the larger of the two values as the initial count. Incremental results are stored in alternate register pairs. The power-on hour meter may be reset or preset by writing to these registers. These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers.
BYTE 3 2 1 0 POHA, high-byte POHA, low-byte POHB, high-byte POHB, low-byte Weight
OEM Scratchpad Registers (SCRATCHn) Default Value Serial Address Byte Address 0000 0000b = 00h A6h = 1010011b SCRATCH0: 126 = 7Eh SCRATCH1: 127 = 7Fh SCRATCH2: 128 = 80h ....................................... SCRATCH127: 253 = FDh
The scratchpad registers are general-purpose non-volatile memory locations. They can be freely read from and written to any time the MIC3001 is in OEM mode. RX Power Look-up Table (RXLUTn) Default Value Serial Address Byte Address 0000 0000b = 00h A6h = 1010011b 40-71 = 28h - 47h
These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers.
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BYTEs RXSLP0h RXSLP0l RXOFF0h RXOFF0l RXSLP1h RXSLP1l RXOFF1h RXOFF1l * * * RXSLP7h RXSLP7l RXOFF7h RXOFF7l RX Slope 0, High Byte RX Slope 0, Low Byte RX Offset 0, High Byte RX Offset 0, Low Byte RX Slope 1, High Byte RX Slope 1, Low Byte RX Offset 1, High Byte RX Offset 1, Low Byte * * * RX Slope 7, High Byte RX Slope 7, Low Byte RX Offset 7, High Byte RX Offset 7, Low Byte Definition
Micrel
Calibration Constants (CALn) Default Value Serial Address Byte Address 0000 0000b = 00h A6h = 1010011b 74 - 87 = 4A h - 57h
These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers.
BYTEs TOFFh TOFF0l VSLP0h VSLP0l VOFFh VOFF0l ISLP0h ISLP0l IOFFh IOFF0l TXSLPh TXSLPl TXOFFh TXOFFl Temperature Offset, High Byte. Temperature Offset, Low Byte. Always Reads Zero; Writes Ignored. Voltage Slope, High Byte. Voltage Slope, Low Byte. Voltage Offset, High Byte. Voltage Offset, Low Byte. Bias Current Slope, High Byte. Bias Current Slope, Low Byte. Bias Current Offset, High Byte. Bias Current Offset, Low Byte. TX Power Slope, High Byte. TX Power Slope, Low Byte. TX Power Offset, High Byte. TX Power Offset, Low Byte. Definition
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Manufacturer ID Register (MFG_ID) Identifies Micrel as the manufacturer of the device. Always returns 2Ah D[7] read only 0 Default Value Serial Address Byte Address D[6] read only 0 D[5] read only 1 D[4] read only 0 0010 1010b = 2Ah A6h = 1010011b 254 = FEh D[3] read only 1 D[2] read only 0 D[1] read only 1
Micrel
D[0] read only 0
The value in this register, in combination with the DEV_ID register, serve to identify the MIC3001 and its revision number to software. This register is read-only.
Bit(s) Function Operation
D[7:0]
Identifies Micrel as the manufacturer of the device. Always returns 2Ah.
Read only. Always returns Ah
Device ID Register (DEV_ID) D[7] read only D[6] read only D[5] read only D[4] read only D[3] read only D[2] read only DIE REVISION 0001 xxxxb = 1xh A6h = 1010011b 255 = FFh D[1] read only D[0] read only
MIC3001 DEVICE ID always reads 0 at D[5-7] and 1 at D[4] Default Value Serial Address Byte Address
The value in this register, in combination with the MFG_ID register, serve to identify the MIC3001 and its revision number to software. This register is read-only.
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Micrel
Applications Information
Controlling Laser Diode Bias
MIC3001
RFB
To ADC
VMPD
FB
VDD
VDDA
RBASE APCDAC
VBIAS
From laser driver Q1 PNP VDD L1 LDA IMOD MDC
CCOMP
COMP
To ADC
VILD+
LDC/MDC
VILD-
L2
SHDN
Redundant Switch (optional)
RSENSE
Figure 26. Example APC Circuit for Common-Cathode TOSA
VDD
RSENSE MIC3001 Redundant Switch (optional)
SHDN
L2 LDC/MDC
To ADC
VILD- VILD+
VDDA
VDD
L1 LDA Q1 PNP MDC IMOD
APCDAC
RBASE
VBIAS
CCOMP
COMP
To laser driver
FB
RFB
To ADC
VMPD
Figure 27. Example APC Circuit for Common Anode TOSA
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Choosing CCOMP The APC loop is compensated by a capacitor, CCOMP, connected from COMP to either VDDA or GNDA. This capacitor adjusts the slew rate and bandwidth of the loop as follows:
SlewRate = dV / dt = BW = GM 2CCOMP ISLEW CCOMP
Micrel
Application 8b/10b encoding, 1Gbps, tON 1ms SONET (62b/64b encoding), 1Gbps 155Mbps, tON 1ms 155Mbps Table 22. Typical Values for CCOMP While there is no theoretical upper limit on the size of CCOMP, it is desirable for the loop to be able to track the changes resulting from periodic temperature compensation. The typical temperature compensation update period is 1.6s. Therefore, a maximum size of 1F is recommended. If laser turnon time is not a factor, a value between 100nF and 1F can be used for virtually any typical application. The tradeoff is that higher value capacitors have a larger physical size and cost. In order to maximize the power supply rejection ratio (PSRR), CCOMP should be returned to GNDA when the VBIAS output is sourcing current, e.g., driving an NPN transistor (SRCE bit = 1). CCOMP should be returned to VDDA when the VBIAS output is sinking current, e.g., driving a PNP transistor (SRCE bit =0). Measuring Laser Bias Current VILD+ and VILD- form a pair of pseudo-differential A/D inputs for measuring laser diode bias current via a sense resistor. The signal applied to these inputs is converted to a single-ended, ground-referenced signal for input into the ADC and bias current fault comparator. These inputs have limited common-mode voltage range. The full-scale differential input range is VREF/4 or about 300mV. Figure 26 and Figure 27 illustrate the typical implementation of this function. Note that VILD- is always connected to the circuit's reference potential: VDD in the case of a commonanode transmitter optical sub-assembly (TOSA) and GND in the case of a common-cathode TOSA. Note that the monitor photodiode current will also flow in the sense resistor. This will result in a small offset in the measured bias current. The APC function will hold this term constant, so it can be corrected for in the external calibration constants. The sensing resistor could also be connected between VDD and the emitter of Q1 on figure 26 or between the emitter of Q1 an GND on figure 27. Interfacing To Laser Drivers In order for the MIC3001 to control the modulation current of the laser diode, an interface circuit may be required depending on the method used by the driver to set its modulation current level. Generally, most laser diode driver ICs use one of three methods: a) A current, ISET, is sourced into a pin on the driver IC. The modulation current delivered by the driver is then some fixed multiple of ISET. The SY88912 is an example of this type of driver. A simple circuit can be used to create a current source controlled by the VMOD outputs. The circuit is based on an external bipolar transistor and a current sensing resistor. 68 August 2004 CCOMP (nF) 10 22 22 100
where: ISLEW = 64A, GM = 125Mho these relationships are shown graphically in Figure 28 and Figure 29.
70 60
SLEW RATE (mV/ s)
50 40 30 20 10 0 1 6 11 16 21 26 31 36 41 46 51 CCOMP (nF)
Figure 28. Slew Rate vs. CCOMP Value
2.50 2.00 1.50 1.00 0.50 0 10 20 30 40 50 60 70 80 90 100 CCOMP (nF)
Figure 29. Open Loop Unity-Gain Bandwidth vs. CCOMP The loop response should be tailored to the data rate, encoding format and maximum run-lengths, and required laser turn-on time. Higher data rates and/or shorter maximum run lengths and/or faster turn-on times call for smaller capacitors. Lower data rates and/or longer maximum run lengths and/or slower turn-on times call for larger capacitors. In order to meet the SFP/GBIC turn-on requirement of 1ms, for example, do not employ a capacitor larger than 20nF. Low ESR capacitors such as ceramics will give the best results. Excessive ESR will reduce the effectiveness of CCOMP. The capacitor's voltage rating must exceed VDDA. Some typical values are shown in Table 22.
M9999-082404
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MIC3001
b) A current, ISET, is drawn out of a pin on the driver IC. The modulation current delivered by the driver is then some fixed multiple of ISET. A simple circuit can be used to create a current source controlled by the VMOD outputs. The circuit is based on an external bipolar transistor and a current sensing resistor. c) A voltage, VSET, is applied to a pin on the driver IC. This voltage may be referenced to GND or VDD. The MIC3001's VMOD+ output can supply this voltage directly. If a voltage swing wider than VREF is needed, gain can be applied with a pair of external resistors. The SY88932, SY88982, and SY89307 are examples of this type of driver. SY88912 3.3V 3.2Gbps SONET/SDH Laser Driver The modulation level of the SY88912 driver is controlled by the current sourced into the RSET pin (Type (a) above). The circuit shown in Figure 30.allows the MIC3001's VMOD outputs to control the SY88912's modulation current from its minimum value, 5mA, to its maximum value, 60mA. The circuit operates as a DAC-controlled current source. The current source is formed by the VMOD buffer amplifier, external transistor, and current sense resistor. The op-amp acts to force the voltage drop across RSET to be equal to the DAC output voltage. The current, ISET, through RSET is therefore regulated as ISET = VMOD+/RSET (In this case, the DAC output and therefore the op-amp output, are referenced to VDDA.) The SY88912's current gain, IMOD/ISET, is 23. A modulation current level of 60mA requires ISET = 60mA/23 = 2.61mA; a modulation current level of 5mA requires ISET = 5mA/23 = 0.217mA. RFLTR and CFLTR are optional and act to eliminate any noise that might be present on VDDA or VMOD. The values shown give a 100s time constant. Note that the time constant is present whenever the laser is turned on or turned off. This must be taken into account when designing to system specifications such as the SFP MSA's tON and tOFF requirements. The values of RFLTR and/or CFLTR may need to be adjusted accordingly. The impact of the filter time constant on the turn off time can be eliminated by using the MIC3001's SHDN signal to drive the SY88912's enable input, /EN. The use of the SHDN signal is completely optional. The main benefit to using SHDN, however, is that it shuts down the driver very quickly and irrespective of the values of RFLTR and CFLTR. The values of RFLTR and CFLTR can therefore be increased, enhancing their effect without incurring any turnoff time penalty. Depending on the polarity chosen for SHDN using the SPOL bit, an inversion may be required between the MIC3001's SHDN output and the driver's /EN input. (The SHDN output may also be used to drive a redundant safety switch and the same polarity may not be appropriate for both functions.)
MIC3001 VDDA VDD(1)
Micrel
SY88912
CFLTR 100nF RFLTR 1k
RSET 420 Q1 2N3906 RSET
MODDAC
VMOD+
ISET x23 IMOD
GNDA MODREF bit = 1 VMOD- SHDN Optional - see text Notes: 1. Bypass capacitors not shown for clarity.
GND
/EN
Figure 30. Controlling the SY88912 Modulation Current For the circuit of Figure 30, the modulation current control range and corresponding DAC values are shown in Table 23 below.
DAC VALUE 0 19 127 255 VDDA - VMOD 0V 0.091V 0.61V 1.22V ISET 0mA 0.216mA 1.45mA 2.91mA IMOD 0mA 4.98mA 33.4mA 66.8mA
Table 23. Control Range of SY88912 Modulation Control Circuit SY88932 3.3V 3.2Gbps SONET/SDH Laser Driver The modulation level of the SY88932 driver is controlled by the voltage applied to the VCTRL pin (Type (c) above). The circuit shown in Figure 31 allows the MIC3001's VMOD output to control the SY88932's modulation current. The circuit operates as a DAC-controlled voltage source. VCTRL is simply the DAC output voltage. See section above on SY88912 for RFLTR, CFLTR and SHDN.
MIC3001 VDDA RFLTR 1k VMOD+ VCTRL CFLTR 100nF GNDA MODREF bit = 0 VMOD- SHDN Optional - see text Note: 1. Bypass capacitors not shown for clarity. /EN GND VDD(1) SY88932 VCC IMOD
MODDAC
Figure 31. Controlling the SY88932 Modulation Current
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SY89307 5.0V/ 3.3V 2.5Gbps VCSEL Driver The modulation level of the SY89307 driver is controlled by the voltage applied to the VCTRL pin (Type (c) above). The circuit shown in Figure 32 allows the MIC3001's VMOD output to control the SY89307's output swing. VCTRL is simply the DAC output voltage. The circuit operates as a DAC-controlled voltage source. See section above on SY88912 for RFLTR, CFLTR.
MIC3001 VDDA CFLTR 100nF VCTRL VDD(1) SY89307 MODREF bit = 1 VCC SHDN MODDAC VMOD+ RFLTR 1k Optional - see text Notes: 1. Bypass capacitors not shown for clarity /EN VDD(1) MIC3001 VDDA MODDAC RFLTR 1k VMOD+ CFLTR 100nF VDD RSET Q1 2N3906 RSET
Micrel
LD Driver
ISET x23 IMOD
GNDA VMOD-
GND
GNDA MODREF bit = 1 VMOD-
VEE
Figure 33. Controlling the Modulation Current via a Sink Current Drivers With Monitor Outputs Laser diode driver ICs have been introduced with monitor outputs. These outputs provide ground-referred signals that mirror critical signals like laser bias current, modulation current or monitor photodiode current, an analog of transmitted power. Generally, these outputs source a current into an external resistor to generate a ground referenced voltage. Using these outputs with the MIC3001 is straightforward since the MIC3001's VILD+/- and VMPD inputs are polarity programmable, Shutdown Output The shutdown output, SHDN, can be used in two ways: as an enable or on/off control for the laser driver IC, and/or to control a redundant switch in the laser current path. The redundant switch provides a means for the MIC3001 to shut off the laser current even if the bias transistor or modulator is damaged or fails. SHDN is active any time the MIC3001 shuts down the laser, i.e., if the TXDISABLE function is asserted in hardware or software, or if the fault detection circuits trigger laser shutdown. The shutdown output, SHDN, is essentially a logic output with programmable polarity. The programmable polarity allows SHDN to drive either high-side or low-side switches or active-high or active-low enable inputs without the need for external inversion circuits. If an active-low and an active-high shutdown signal are required, an external inverter will be necessary. Examples of redundant switch circuits are shown in Figure 34.
Note: 1. Bypass capacitors not shown for clarity.
Figure 32. Controlling the SY89307 Modulation Current Laser Drivers Programmed via a Sink Current The modulation level of some laser diode drivers is controlled by a current sourced out of the RSET pin (Type (b) above). The circuit shown in Figure 33 allows the MIC3001's VMOD outputs to control the set current, ISET. The circuit operates as a DAC-controlled current sink. The current sink is formed by the VMOD buffer amplifier, external transistor, and current sense resistor. The op-amp acts to force the voltage drop across RSET to be equal to the DAC output voltage. The current through R SET is therefore regulated as IRSET = VMOD+/RSET. ISET is given by the equation:
VMOD + ISET = R SET 1+
(13)
where is the DC gain of Q1 The higher the gain of the transistor, the closer ISET will be to the current in RSET. RFLTR and CFLTR act to eliminate any noise that might be present on VDDA or VMOD. The values shown give a 100s time constant. See section above on SY88912 for RFLTR, CFLTR and SHDN.
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VDD High-Side VDD
Micrel
Remote Sensing For remote temperature sensing using the XPN pin, most small-signal PNP transistors with characteristics similar to the JEDEC 2N3906 will perform well as thermal diodes. Table 24 lists several examples of such parts that Micrel has tested for use with the MIC3001. Other transistors equivalent to these should also work well.
Vendor Fairchild Semiconductor
Q1 NPN RPULLDOWN SHDN RPULLUP Q1 N-FET
RPULLUP
RPULLUP
SHDN
RBASE
Q1 PNP
SHDN
Q1 P-FET ILD
ILD ILD RBASE Low-Side
ILD
Part Number MMBT3906 MMBT3906L SMBT3906/MMBT3906 KST3906-TF
Package SOT-23 SOT-23 SOT-23 SOT-23
SHDN
On Semiconductor Infineon Technologies Samsung Semiconductor
GND
GND
Figure 34. Redundant Switch Circuits Temperature Sensing The MIC3001 can measure and report its own internal temperature or the temperature of a remote PN junction or "thermal diode". In either case it is important to note that any board-mounted semiconductor device tends to track the ground plane temperature around it. The dominant thermal path to the sensor is often the ground pin. The ground pin usually connects to the leadframe paddle on which the die is mounted. Typical semiconductor packages, being non-conductive plastic, insulate the device from the ambient air. The advantage to using a remote sensor is that the temperature may be sensed at a specific location, such as in the proximity of the laser diode, or away from any heat sources where it will more closely track the transceiver's case temperature. The measured temperature is reported via the digital diagnostics registers and is used to index the temperature compensation tables. (Note: SFF-8472 does not specify the meaning of the reported temperature information or the location from which it is taken. This information is to be specified in the transceiver vendor's datasheet.)
Table 24. Transistors Suitable for Use as Remote Diodes
Minimizing Errors
Self-Heating One concern when measuring temperature is to avoid errors induced by self-heating. Self-heating is caused by power dissipation within the MIC3001. It is directly proportional to the internal power dissipation and the junction-to-ambient thermal resistance, JA. The dissipation in the MIC3001 must be calculated and reduced to a temperature offset. The power dissipation, PDISS, includes the effect of quiescent current and all currents flowing into or out of any signal pins, especially VBIAS and VMOD. The temperature rise caused by selfheating is given by:
t = PDISS x JA
(14)
JA is given in the "Operating Ratings" section above as 43C/W. The possible contributors to self-heating are listed in Table 25. The numbers given in Table 25 suggest that the power dissipation in a typical application will be no more than a few tens of milliwatts, leading to self-heating on the order of 1C.
Description Quiescent power SHDN current TXFAULT current VBIAS current VMOD current RSOUT current DATA current RXLOS current
Magnitude IDD x VDD IOL x VOL IOL x VOL VBIAS x IVBIAS or (VDD-VBIAS) x IVBIAS VMOD x IVMOD or (VDD-VMOD) x IVMOD IOL x VOL IOL x VOL x duty_cycle IOL x VOL
Notes Typically VDD = 3.3V, IDD = 2.7mA 3.3V x 2.7mA = 8.91mW. Negligible if MOSFET is used as shutdown device. Worst case is VDD2/RPULLUP; RPULLUP is 4.7k min. per SFP MSA 3.3V2/4.7k = 2.32mW. Worst-case is VREF x 10mA = 1.22V x 10mA = 12.3mW. Worst-case is VREF x 10mA = 1.22V x 10mA = 12.3mW. Only for rate-agile applications using RSIN/RSOUT. May be negligible; Depends on bus speed, pullup current, and bus activity. Worst case is VDD2/RPULLUP; RPULLUP is 4.7K min. per SFP MSA 3.3V2/4.7k = 2.32mW.
Table 25. Contributors to Self-Heating
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In any application, the best and often easiest approach is to measure performance in the final application environment. This is especially true when dealing with systems for which some temperature data may be poorly defined or unobtainable except by empirical means. If desired, the external calibration constants may be used to correct the temperature readings. Series Resistance with External Temperature Sensor The operation of the MIC3001 depends upon sensing the VCB-E of a diode-connected PNP transistor ("diode") at two different current levels. For remote temperature measurements, this is done using an external diode connected between XPN and ground. Since this technique relies upon measuring the relatively small voltage difference resulting from two levels of current through the external diode, any resistance in series with the external diode will cause an error in the temperature reading from the MIC3001. A good rule of thumb is this: for each ohm in series with the external transistor, there will be a 0.9C error in the MIC3001's temperature measurement. It is not difficult to keep the series resistance well below an ohm (typically <0.1), so this will rarely be an issue. XPN Filter Capacitor Selection It is desirable to employ a filter capacitor between XPN and GNDA. The use of this capacitor is especially recommended in environments with a lot of high frequency noise (such as digital switching noise), or if long wires are used to connect to the remote diode. The maximum recommended total capacitance from the XPN pin to GND is 2000pF. The recommended typical capacitor is a 1000pF NP0 or C0G ceramic capacitor with a 10% tolerance. If the remote diode is to be at a distance of more than 6" to 12" from the MIC3001, using twisted pair wiring or shielded microphone cable for the connections to the diode can significantly reduce noise pickup. If using a long run of shielded cable, remember to subtract the cable's conductor-to-shield capacitance from the 2000pF maximum total capacitance. XPN Layout Considerations The following guidelines should be kept in mind when designing and laying out circuits using the MIC3001 and a remote thermal diode: 1. Place the MIC3001 as close to the remote diode as possible, while taking care to avoid severe noise sources such as high speed data busses, and the like. 2. Since any conductance from the various voltages on the PC board and the XPN line can induce errors, it is good practice to guard the remote diode's emitter trace with a pair of ground traces. These ground traces should be returned to the MIC3001's own ground pin. They should not be grounded at any other part of their run. However, it is highly desirable to use these guard traces to carry the diode `s own ground return back to the ground pin of the MIC3001, thereby providing a Kelvin connection for the base of the diode.
Micrel
3. When using the MIC3001 to sense the temperature of a processor or other device which has an integral thermal diode, connect the emitter and base of the remote sensor to the MIC3001 using the guard traces and Kelvin return shown in Figure 35. The collector of the remote diode is typically inaccessible to the user on these devices. 4. Due to the small currents involved in the measurement of the remote diode's VBE, it is important to adequately clean the PC board after soldering to prevent current leakage. This is most likely to show up as an issue in situations where water-soluble soldering fluxes are used. 5. In general, wider traces for the ground and T1 lines will help reduce susceptibility to radiated noise (wider traces are less inductive). Use trace widths and spacing of 10 mils wherever possible and provide a ground plane under the MIC3001 and under the connections from the MIC3001 to the remote diode. This will help guard against stray noise pickup.
MIC3001 GNDA XPN
GUARD/RETURN REMOTE DIODE (XPN) GUARD/RETURN
Figure 35. Guard Traces and Kelvin Return for Remote Thermal Diode Layout Considerations
Small Form-Factor Pluggable (SFP) Transceivers
The pinout of the MIC3001 digital control and status signals was optimized for use in small form-factor pluggable (SFP MSP) optical transceivers. If the MIC3001 is mounted on the bottom of the PC board with the correct rotation, the control and status I/O can be routed to the host connector without changing the order. This is shown in Figure 36 below.
VCCR 1 2 3 4 5 6 7 8 9 10 11 12 TOP VIEW 24 23 22 21 20 19 18 17 16 15 14 13 VCCR LOS RATESEL MOD-DEF (0) CLOCK DATA TXDISABLE TXFAULT VCCT
Figure 36. Typical SFP Control and Status I/O Signal Routing (not to scale)
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Power Supplies The MIC3001 has separate power supply and ground pins for both the analog and digital supplies. This helps prevent digital switching noise from corrupting the analog functions. The individual supply and ground pins are not isolated from one another inside the IC. Separate analog and digital power and ground planes are NOT required on the PCB. Having one of each plane (power and ground) is certainly good practice, however. If dedicated power and ground layers are not available, care should be taken to route the digital supply and return currents back to the supply separate from the analog supply connections. A schematic of this approach is shown in Figure 37. Each supply should be bypassed as close to the IC as possible with 0.01F capacitor (Low ESR capacitors such as ceramics are preferred.) as shown. This assumes that bulk capacitance is already present upstream. If no other filter capacitance is present nearby, a 1F filter capacitor should be added in parallel to the 0.01F capacitor.
HOST P/S (+)
Power Plane
Micrel
Using The MIC3001 In a 5V System It is fairly straightforward to use the MIC3001 in a system powered from a 5V rail. In these systems, the laser diode driver IC will usually be powered from the 5V rail. A small linear regulator, such as Micrel's MIC5213, can be used to generate a 3.3V power supply rail if one does not otherwise exist in the system. All of the MIC3001's digital I/O's except for RSOUT are 5V tolerant and may be pulled up to 5.5V regardless of the MIC3001's supply voltage. They can be connected directly to a 5V host. The MIC5213 is ideal, as it is capable of supplying up to 80mA, is in a tiny SC-70 package, and is stable with small ceramic output capacitors. The laser diode driver interface will be unchanged in most cases. Ground referred voltages and currents can be generated the same way as with 3.3V-powerd drivers. The exception is drivers that are controlled by a voltage referenced to VDD such as the SY89307. The MIC3001's VBIAS or VMOD output will be referenced to its own 3.3V power supply whereas the driver's input will be referenced to its 5V power supply. The solution is a simple level-shifting circuit that converts the VBIAS/VMOD output into a current and then into a VDD-referenced voltage.
VDDD C1 1.0F
(1)
VDDA C3 0.01F
(1)
C2 0.01F
MIC3001 GNDD GNDA
C4 1.0F
Ground Plane
HOST P/S (-)
Figure 37. Power Supply Routing and Bypassing
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Package Information
24-Pin MLFTM (ML)
MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2004 Micrel, Incorporated.
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